Course #36

Silicon Device Technology: Materials and Processing Overview

October 18-22, 2010. Dresden, Germany 

INSTRUCTORS
Professor Tim J. Anderson, University of Florida, Gainesville, USA
Professor Paul S. Ho, University of Texas, Austin, USA
Dr Roel Gronheid, IMEC, Leuven, Belgium
Dr  Gilles Cunge, LTM/CNRS, Grenoble, France
Mr Christopher McDonald, Applied Materials, Austin, USA, 
Dr Jeffrey Gambino, IBM Microelectronics, Essex Junction, USA  

TECHNOLOGY FOCUS 
The rapid growth of the semiconductor industry has relied on the continual evolution of materials and processing compatible with fabricating modern silicon-based integrated circuits. Several technologies are emerging to meet the demands for higher speed and density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology with both Separation by Implantation of Oxygen (SIMOX) and wafer bonding approaches are now commercially available. 

COURSE CONTENT 
This course will provide an overview of the entire fabrication process. It will include all the key materials involved and the process areas utilized in device manufacturing.This course is thus addressed to a broad audience and is not intended as a research review, although it will be taught at a high level and in many areas requires familiarity with the subject matter. 

Monday – TIM ANDERSON 

Si Front-end Manufacturing 
The entire front-end manufacturing process will be presented. 
A perspective on process bottlenecks and future 
trends, as outlined in the most recent ‘International Technology 
Roadmap for Semiconductors’, is presented. 

• Si Wafer Production
• Epitaxy 
• Oxidation 
• Dielectric Deposition
• Ion Implantation
• Metallization 
• Lithography
• Etching 

• Electrical, Optical, and Structural Properties of Silicon 
• Control of the Point and Extended Defect Densities 
• Origin of Defects and Their Influence on Device Performance 
• IC Materials Characterization for Process Improvement and Achieving High Yield 

Process Induced Defects and Device Performance 
Common impurities introduced during crystal growth and their influence will be discussed.The crystallography of the diamond structures and the formation mechanisms and structures of extended defects, i.e. stacking faults, misfit dislocations, twins, will be reviewed. Both intrinsic and extrinsic gettering technologies will be described with a discussion of their effects on subsequent device processing and device parameters. 

Large Diameter Wafers 

It is essential to have the highest quality Si wafers to achieve high process yields. The wafering process and issues related to quality assurance and acceptance will be addressed. 

SIMOX, Wafer Bonding, SiGe and Other Emerging Technologies 
Several technologies are emerging to meet the demands for higher speed, higher density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology, with both SIMOX and wafer bonding approaches, are now commercially available. Promises and limitations of SOI will be presented to ease the decisions in wafer specification. 

The SiGe1-x alloy is another advanced material that is xcurrently emerging into the marketplace. These alloys allow the properties of Si to be engineered through composition control. Applications include intrinsic gettering through strain field control and high-speed devices. The impact of the growth process on the properties and an overview of the device applications will be presented. 

Silicon Epitaxy by CVD 
Silicon epitaxial deposition is a strategic process technology in large volume manufacturing. The understanding and control of this technology is critical to the success of the production of high quality devices and circuits. 

• Substrate Crystal Orientation, Deposition Parameters, and Choice of Silicon Source Material 
• CVD Fundamentals for Si Deposition Chemistries 
• Reactor Design to Illustrate Deposition Mechanisms 
• The Influence of Deposition Parameters on Film Quality 
• Procedures to Prepare Wafers for Epitaxy 
• Film Quality and Device Performance 
• Si Etching by Wet Processes 
• Isotropic and Anisotropic Etchants 

Tuesday – TIM ANDERSON/PAUL HO 

Silicon Oxidation 
The role of the native oxide of Si as an enabler of VLSI technology cannot be overstated.This section outlines the fundamental aspects of silicon oxidation.

• Gate Oxide, Surface Passivation, Mask, Device Isolation 
• Growth Models for Wet and Dry Oxidation 
• Surface Preparation 
• Charge and Atom Transport 
• Dopant Redistribution 
• Orientation Effects 
• Properties of Ultra-thin Oxides 
• Novel Processes such as Rapid Thermal Oxidation

Deposition of Metals and Dielectrics by Physical and Chemical Methods 
The various physical and chemical approaches to the deposition of metal and dielectric materials are outlined and compared. The ‘Roadmap’ predicts that Atomic Layer Deposition (ALD) methods will eventually become the dominant 
process because it is well suited for deposition of ultra-thin, highly conformal films over small device features.

Integrated Circuit Metallization Systems 

• Multilayered Interconnect Structures: High density and high performance 
• Scaling and Wiring Requirements of ULSI Circuits 
• Interconnect Performance and Density 
• Requirements for Metallization Systems in Device Contacts and Interconnecting Lines 
• Major Factors Affecting Reliability of Multilayered Sub-micron Interconnects 
• New Interconnects with Cu and Low k Material 

Dielectrics for Multilayered Metallization 

• Thin Film Dielectrics 
• The Evolution of Interlevel Dielectrics from SiO2 to Low k Dielectrics 
• Material Requirements and Integration Issues 
• Development of Organic and Inorganic Low k Materials 
• Tradeoff of Thermo-Mechanical Properties 
• Impacts on Reliability 

Wednesday – TIM ANDERSON/ROEL GRONHEID 

CMP for Microelectronics Applications 
Chemical Mechanical Planarization (CMP) is an enabling technology for the microelectronics industry. The empirical nature of CMP and how it bridges many engineering disciplines for resolution of its numerous challenges will 
be emphasized. 

• How to Effectively Utilize CMP 
• Evolution and Revolution of CMP Equipment and Consumables 
• Characterization Techniques for Process Development and Control 
• Advantages and Limitations of CMP Processes for 
• Advanced Microelectronics Applications 

High k Dielectric Materials 
Alternate gate dielectric materials are being developed, as the continuously reduced SiO2 thickness is approaching its physical limitation and direct electron tunneling results in unacceptably high leakage currents. 

• Potential High k Materials Ranging from 10 to 100: Transition metal oxides, ferroelectric materials, metal silicates 
• The Impact of Thin Gate Oxides on Device Performance 
• Benefits of the Use of High k Dielectrics 
• Material Properties, Growth Methods, and Impact on Device Performance 

Optical Lithography 
The continuous trend of miniaturization in IC manufacturing and the importance of lithography as an enabling technology will be presented. 
Optical lithography has till now always been the workhorse of the industry. The lithographic process of optical lithography will be analyzed. 

• Image Formation in the Optical Lithography Process 
• Basics of the Resist Chemistry 
• Issues Encountered when Applying Resists to Real Device Processing 
• Resolution Enhancement Techniques: Phase shifting masks, off-axis illumination, optical proximity correction 

Recently, immersion lithography has been introduced as a next technique to further scale down the resolution limits of optical lithography.This course will also address the fundamentals of immersion lithography, give an update of the 
issues and status, and finally give an outlook to the ultimate resolution limits using immersion lithography. 

Thursday – GILLES CUNGE/JEFFREY GAMBINO 

Plasma Etching and Plasma-Enhanced CVD 

• Reactive Gas Glow Discharges: Plasma etching, reactive ion etching, and PECVD 
• Operation of Low and High Density Plasma Sources 
• Surface Science Aspects of Plasma Etching 
• The Role of Energetic Ion Bombardment in Obtaining Etch Profile Anisotropy 
• Etching of Silicon and Its Compounds in Halogen-based Etching 
• PECVD and Its Role in Plasma Etching 
• PECVD Processes of Greatest Importance in Semiconductor Manufacturing 

Ion Implantation and Diffusion 
Critical issues of ion implantation and junction formation in silicon devices are discussed. 

• Process Issues in Applying Ion Implantation/Annealing 
• Materials Issues of Ion Penetration, Damage Production, and Masking 
• Annealing Implanted Layers in Silicon: Oxidation over implanted layers, furnace annealing, Rapid Thermal Processing (RTP) 
• Critical Issues for Creating pn Junctions in Silicon: Low leakage junctions, removing damage, controlling diffusion during the annealing of implantation damage, scaling of pn junction depths, contacting, diffusion through thin oxides in doped polysilicon gate/oxide/ silicon devices 
• Process Simulation for Design and Control of Implanted and Annealed Junctions 

Friday – CHRISTOPHER MCDONALD 

Reliability and Yield 
The success of an IC manufacturing facility is directly connected to IC reliability and product yield. An overview of failure mechanisms and yield limitations will be presented. The discussion will include approaches to circuit and layout design, device design, materials selection, process optimization, as well as thermo-mechanical considerations. Proven yield improvement management processes will be outlined. 

Regular Course Fee: EUR 2995

Early Registration Course Fee: EUR 2725
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches etc.) paid on your behalf to the course venue. Accommodation is not included.