Course #55

Signal Integrity: Advanced High-Speed Design and Characterization

October 4-8, 2010. Copenhagen, Denmark

(See also course #56, www.cei.se/056.htm)

INSTRUCTOR
Dr. István Novák, Oracle., Boston, USA

TECHNOLOGY FOCUS
High-speed designs continue to undergo major technology changes. In recent years, parallel signaling rates exceed 1000 Mbps and main-stream serial signaling is in the 5-10 Gbps range; signal rise and fall times shrink to way below 100 ps. As a result, interconnect losses, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be understood and taken into account during the design process. With the increasing utilization of transmit and receive equalizations, validation even with eye diagrams measured at package pins may not be sufficient in itself. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages and signaling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects eventually link the previously independent power-integrity, signal-integrity and EMC design domains. 

COURSE CONTENT
This renewed course uses a series of dedicated HW and software illustrations and design examples to show and explain major rules of proper signal-integrity design. The course gives guidance to properly select medium- and low-loss laminates, stackup and layout to ensure good signal integrity without expensive over-design. The class focuses on signal integrity in board and system interconnects with the necessary brief overview of power-integrity and EMC design principles. Detailed power-integrity design and validation is covered in the companion course #56; Power Integrity: Advanced Design and Characterization. 

The HW and SW illustrations are shown live during the class. The teaching methodology is based on showing and explaining good and bad design choices, discussing pros and cons of options and focusing on manufacturability and robust performance. The course is taught with minimal mathematics, relying on the physical phenomena and a few easy-to-remember basic rules. For high-speed signal transmission, emphasis is put on the dispersive and lossy nature of cables, PCB and package traces, showing the link between rise-time degradation, jitter, eye closure and the frequency-domain scattering and transfer parameters. For power distribution and EMC, emphasis is put on the proper impedance profile of the bypass network and how to estimate and compare the worst-case transient noise of various design methodologies. Case studies and simple exercises make the learning experience complete.

Participants will receive several of the tools and simulation files shown in the class.


Monday

Single and Multiple Unloaded Interconnects

• Signal Spectrum, Time and Frequency-domain Solutions 
• Characteristic Impedance, Delay and Performance Regions of Interconnects
• Matching and Termination Solutions and Rules; Allowable Mismatch 
• Time and Frequency Domain Solutions, Network Matrices
• Crosstalk and Crosstalk-reduction in Time and Frequency Domain 
• PCB Construction Rules, Stackup Options and Limitations, Cost and Reliability Considerations

Tuesday

Differential, Multi-Line and Lossy Interconnects

• Differential Interconnects, Effects of Imbalance, Mixed-mode S Parameters, Mode Conversion, Glass.weave Effects
• Multi-line Crosstalk, Simultaneous Switching Noise 
• Multi-drop and Point-to-point Interconnect Characteristics, Loaded-line Filtering
• Skin Loss, Dielectric Loss, Surface Roughness, Laminate Choice and Selection - How low-loss laminates can hurt us
• Discontinuities, Through Holes and Vias, Bends, Stubs 

Wednesday

Clock and Signal Distribution

• Grounding, Shielding and EMI Rules 
• Clock Sources and Drivers, Clock PLLs, Spread-spectrum Clock
• Clock Distribution, Skew, Jitter, Layout and Power-supply Rules to Minimize Jitter
• Jitter Tolerance and Jitter Transfer 
• ISI, Eye Diagram, Peak Distortion Analysis, Linear Network Solutions 

Thursday

System Design

• Parasitics of RLC Components, Integrated Passives
• Cascading High-speed Interconnect Building Blocks
• Component Placement, Stackup and Layout Optimization
• Design of Power Distribution Networks for High-speed Signaling
• Power Distribution Vias, Planes, Bypass Capacitors

Friday

Simulation, Measurement, Validation

• Rules for Creating and Validating Simulation Models
• Rules to Select Simulation Tools, Settings and Setups
• Signal-integrity and Power-integrity Simulations
• Selecting Probes, Cables and Instruments for Signal-integrity Measurements
• Characterization and Validation of High-speed Systems 
• Example: Anatomy of Simulation Accuracy

See also the companion course #56, "Power Integrity: Advanced Design and Characterization", November 22-26, 2010 in Barcelona, Spain

Regular Course Fee: EUR 2995 

Early Registration Course Fee: EUR 2725
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches, etc.) paid on your behalf to the course venue. Accommodation is not included.