Course #56

Power Integrity: Advanced  Design and Characterization

November 22-26, 2010. Barcelona, Spain

INSTRUCTOR
Dr. István Novák, Oracle, Boston, USA

TECHNOLOGY FOCUS
One of the biggest design challenges today is to properly design, manufacture, simulate and validate a Power Distribution Network (PDN) in systems with increasing speed, power dissipation and density. A multitude of supply voltages and signaling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects link the previously independent power-integrity, signal-integrity and Electro-Magnetic Compatibility (EMC) design domains. Eventually, the power distribution design and characterization becomes a corner stone and enabler for good signal integrity and electromagnetic compatibility.

COURSE CONTENT
This new five-day course is devoted entirely to power distribution design and characterization with the necessary brief overview of signal-integrity and electromagnetic compatibility principles. Detailed signal-integrity design and validation is covered in the companion course #55, "Signal Integrity: Advanced High-Speed Design and Characterization". The course is based on a large number of HW and SW illustrations, shown live during the class. The teaching methodology is based on showing and explaining good and bad design choices, discussing pros and cons of options and focusing on manufacturability and robust performance without costly over-design. The course is taught with minimal mathematics, focusing on the physical phenomena and a few easy-to-remember basic rules. 

The course explains the underlying physical rules for successful power distribution designs and shows how the same principles, which can be used to obtain worst-case eye-diagrams in signalling, can also be used to calculate efficiently the worst-case transient noise on power-distribution networks.

In the design process, emphasis is put on the proper impedance profile of the bypass network and how to use the impedance profile to estimate and evaluate the worst-case transient noise of various design methodologies. The class answers (among others) such important questions as what stackup and layout details matter for power distribution, how many and what value of bypass capacitors we need, and where to place bypass capacitors for effective noise suppression. The class will show that placing bypass capacitors close to the active device is not always necessary.

In characterization, equal time is devoted to simulations and measurements. In simulations, different modelling techniques and tools are shown for simulating components, power planes and vias. In measurements, the possible time-domain and frequency-domain instruments are reviewed and the proper set-ups, connections and calibrations are discussed. 

Participants will receive several of the tools and simulation files shown in the class.

Monday

Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility

• Waveforms and Spectra of High-speed Signals and Power Noise
• Interaction of Power Integrity, Signal Integrity and Electromagnetic Compatibility
• Grounding and Shielding Rules, PCB Construction Rules, Laminate Choices
• Unified PDN and SI design: Linear Network Analysis, Sources of PDN Noise
• Impulse and Step Responses, Calculating Worst-case Transient Noise

Tuesday

Power Distribution Components

• DC-DC Converter Properties, Selection, Placement
• Characteristics and Parasitics of Various Bypass Capacitor Types
• Characteristics and Parasitics of Various Decoupling Inductor Types
• Characteristics and Design of Vias and Planes, Thin and Ultra-thin Laminates
• Designing Filters for Low-current Circuits (SerDes, PLL, Vref) 

Wednesday

Power Distribution Design Methodologies

• Choosing the Proper Geometry for DC Power Distribution
• Determining Trace Width for Supply Feeds 
• High-frequency Bypassing with Power-ground Laminates, Stackup Selection, 
• Split Planes and Signal Routing over Splits
• The Procedure of PDN Design, Determining Target Impedance, Point-of-Load PDN Designs from Silicon to DC-DC Converter

Thursday

Component Selection and Placement through Simulations, Multi-Node Design

• Synthesizing PDN Impedance: Multi-pole, Big-V, DMB Approaches
• High-frequency PDN Design, Service Radius of Bypass Capacitors vs. Matched Planes, How to Handle Multiple Supply Rails in the PDN Design
• How to Identify and Eliminate Capacitor-capacitor and Capacitor-plane Antiresonances, The Role and Impact of Package on PDN Performance
• Spreadsheet and SPICE PDN Simulations

Friday

Design and Validation of Power Distribution Networks through Measurements

• Frequency-domain Measurement Set-ups: Two-port shunt-through connections
• measure PDN noise?
• Why we Should Not Measure Noise Across Bypass Capacitors - Considerations for sub-system and full-system PDN measurements.
• Time-domain Measurement Challenges: Uncorrelated external noise, dynamic-range limitations - How to select instruments for PDN testing

See also the companion course #55, "Signal Integrity: Advanced High-Speed Design and Characterization", April 19-23, 2010 in Barcelona, Spain.

Regular Course Fee: EUR 2995

Early Registration Course Fee: EUR 2725
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches, etc.) paid on your behalf to the course venue. Accommodation is not included.

Payment should be made in advance.