Course #61

Yield and Reliability in VLSI Development and Manufacturing

October 18-22, 2010. Dresden, Germany 

INSTRUCTORS
Dr. José A. Maiz, Intel Corporation, Hillsboro, OR, USA
Christopher McDonald, Applied Materials, Austin, TX, USA,  
David Vallett, IBM Systems & Technology Group, Burlington, VT, USA.

TECHNOLOGY FOCUS 
Yield and reliability are two of the cornerstones of a successful IC manufacturing technology along with product performance and cost. Many factors contribute to the achievement of high yield and reliability, and many of these also interact with product performance and cost.
A fundamental understanding of failure mechanisms and yield limitations enables the up-front achievement of these technology goals through circuit and layout design, device design, materials choices, process optimization, and thermo-mechanical considerations. Failure isolation and analysis, defect analysis, low yield analysis, and materials analysis are critical methodologies for the improvement of yield and reliability. Coordination of people in many disciplines is needed in order to achieve high yield and reliability. Each needs to understand the impact of their choices and methods on the final product. Unfortunately, very little formal university training exists in these critical areas of IC reliability, yield, and failure analysis. 

WHO SHOULD ATTEND 
This course will be of strong interest to engineers working in semiconductor R&D and manufacturing, equipment service, and also procurement of product from foundries. It will be relevant both for companies producing integrated circuits themselves and for those involved as partners in the “fabless/foundry” model. 

Monday – JOSÉ MAIZ 

Reliability Fundamentals and Scaling Principles 

• The Reliability Bathtub Curve, Its Origin and Implications 
• Key Reliability Functions and Their Use in Reliability Analysis 
• Defect Screening Techniques and Their Effectiveness 
• Accelerated Testing and Estimation of Useful Operating Life 
• Reliability Data Collection and Analysis in Integrated Circuits 
• Past Technology Scaling Trends 
• Forward Looking Projections with a Focus on Examining and Understanding of the Impact on VLSI Reliability 
• Power Density Trends: Operating temperature, activation energies for dominant vlsi failure mechanisms, and reliability impact 
• Reliability Strategies In Fabless Environments 

Reliability of the Interconnect System 

• Physics and Statistics of Failure Mechanisms Associated with Interconnect Systems 
• Electro-migration of Al and Cu Interconnects 
• Mechanical Stress Driven Metal Voiding and Cracking 
• Low k Materials as Interlayer Dielectrics and Their Impact on Electro-migration 
• Thermo-mechanical Integrity of the Interconnect System 
• Key Technology Parameters: Materials choices, structural and geometric effects 
• Extreme Scaling Impact on Wear-out Time 
• Technology Solutions: Alloys, metal barriers, and engineering of interfaces 
• Improved Electro-migration Performance under Non-DC Currents and Short Lines 
• Interconnect Reliability Strategies in Fabless Environments 

Tuesday – JOSÉ MAIZ 

Transistor Reliability: Dielectric Breakdown, Hot Carriers and Parametric Stability 

• Physics, Statistics, and Scaling Impact on Failure Mechanisms 
• Reliability Performance of Thin Conventional Oxides: Defects, wear-out failures 
• Hot Carrier Performance and Parametric Stability of P- and N-channel Devices under DC and AC 
• High k Gate Dielectrics and Novel Transistor Configurations 
• Key Failure Mechanisms for Bipolar Transistors 
• Transistor Reliability Strategies in Fabless Environments 

CMOS Latch-up and ESD 

• Physics, Scaling Impact, and Technology Dependence of CMOS Latch-up and Electrostatic Damage (ESD) 
• Technology and Design Based Solutions, Device Performance, and Manufacturability Constraints 
• Latch-up and ESD Assessment in Fabless Environments 

Soft Errors, and Other Failure Mechanisms 

• Physics, Scaling Impact, and Technology Dependence of Alpha Particle and Cosmic Ray Induced Soft Errors 
• Technology Solutions, Performance, and Manufacturability 

Wednesday – CHRISTOPHER MCDONALD 

Yield Elements 

• The Importance of Yields to the Financial Success of a Semiconductor Manufacturer 
• Data of Typical Yields Obtained in the Industry for Different Product Generations 
• The Concept of Yield Modeling, Showing Defects and Other Mechanisms Affecting Yields 
• Process and Equipment Defect Details: Lithography, oxidation, thin film deposition, etching, and wafer cleaning 
• Other Defect Sources: Clean-room materials and environment 
• Yield Issues: Electrical parameter distributions and physical device structures 
• Practical Examples: How Yields are Impacted by Various Types of Phenomena 

Yield Management and Improvement 

• Attributes Possessed by“High Yield”Wafer Fabrication Lines 
• In-line Measurement Techniques for Process Control and Improvement: Particle detection and loop structures 
• Examples: Successfully Applied Techniques to Improve Yields 
• The Use, Importance, Application, and Pitfalls of Statistical Process Control 
• Software Techniques for Detecting Significant Patterns in Yield Data 
• Yield Impacting Factors: How continuous improvements can be made 
• Special Topics of Interest 

Thursday – CHRISTOPHER MCDONALD 

Process and Product Control 

• Statistical Process Control 
• Process Certification and Qualification 

Managing Quality in Manufacturing 

• Technology Transfer 
• Copy Exactly 

Design for Manufacturing 

• DFM: What it is and methodology evolution 
• Datamining Techniques: Identify process/product yield interactions and fast troubleshooting 
• Leveraging Mini Shrinks: Improve overall die output 
• Yield Maximization Through Optimizing Product Designs

Fabless/Foundry Model 

• The Fabless/Foundry Business Model 
• Foundry Supplier Selection 
• IP and Design Services 
• Processes for Foundry Supplier Management: Negotiations, planning, inventory 
• Managing Foundry Quality: Supplier management scorecard 

Friday – DAVID VALLET 

Failure Analysis 

• Overview of Failure Analysis Instruments and Processes
• Memory, Logic, Analog, and Mixed Signal Device Approaches 
• Package, Wafer, and Die Level Analytical Strategies
• Methods for Technology Development, Yield, Reliability, and Customer Return Failures 
• Electrical Fault Isolation Principles: Time-domain reflectometry, memory and logic diagnosis
• Physical Fault Isolation Techniques: Electron, ion, and and laser scanning microscopy; photon emission, thermal and magnetic imaging; scanning probe microscopy 
• Electrical Characterization: Micro- and nano-probing 
• Chemical, Mechanical, and Ion Beam Deprocessing 
• Optical, acoustic, scanned probe, electron, and X-ray microscopy/tomography 

Materials Analysis Overview

• Particle Beam Interactions in Solids 
• Bulk Composition Analysis: Energy and wavelength dispersive spectroscopy 
• Principles of Electron, Ion, and X-ray Techniques: TEM, AES, SIMS, XPS, and TXRF 
• Sensitivity and Resolution Comparisons 
• Technique Selection Factors

Practical Applications and Future Challenges 

• Case-histories and Examples: Time-resolved photon emission movies of operating devices; nanoscale 3D X-ray tomography virtual sections; defects; fault isolation results, etc.
• Planning for Analysis to Maximize Effectiveness 
• Scaling and Material Challenges in Analytical Science 

Regular Course Fee: EUR 2995

Early Registration Course Fee: EUR 2725
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches etc.) paid on your behalf to the course venue. 
Accommodation is not included.