Course #62

IC  Debug and Fault Isolation

October 20-21, 2010. Dresden, Germany

INSTRUCTOR
David Vallett, IBM Systems & Technology Group, Burlington, VT, USA.

TECHNOLOGY FOCUS 
Growing IC complexity, especially in a fabless or foundry environment, leads to functionality, yield, or reliability failures that directly affect time-to-market and serviceability. Rapid, definitive root cause determination is realized only through a proactive design, test, and packaging strategy optimized to quickly and accurately diagnose and isolate faults for subsequent failure analysis and corrective action.

Once the domain of a small handful of simple test and failure analysis techniques, this critical field now relies on strong synergy between four key areas: design, test, packaging, and fault isolation - the latter now comprised of a wide array of new, sophisticated electrical and physical instruments and techniques heavily dependent on the first three. The ultimate success of this key element of development and manufacturing hinges on a design, test, and packaging strategy that leverages the capabilities of these new methods while taking into account their dependencies and limitations.

COURSE CONTENT
This course will provide:

• Overview of the debug and fault isolation business and technical environment
• Brief summary of test methodologies and common semiconductor failure mechanisms
• Understanding of leading-edge debug and fault isolation instruments and methods including photonic, thermal, magnetic, electron, ion beam, and x-ray microscopy
• Review of common semiconductor package types and their compatibility with fault isolation techniques
• Case histories and examples
• Guidance on implementing a proactive process for successful debug
• Future challenges.

WHO SHOULD ATTEND 
This course is a thorough introduction for technicians and engineers working directly in quality / reliability, test, and failure analysis, and will also be of value to program managers responsible for quality, sourcing, and procurement in both captive semiconductor fabricator and fabless/foundry environments. 

Wednesday 

The Business and Technical Environment for Debug and Fault Isolation 
The role of debug and fault isolation in IC development and manufacturing is described with an overview of debug strategies, including technical issues and business impacts. Common electrical failure modes and test methodologies for VLSI packages and logic, memory, ASIC, microprocessor, analog, and mixed signal chips are presented and categorized. Most importantly the value of early communication and a design-for-debug strategy between and among stakeholders is emphasized to minimize lost time and expense and maximize supply servicability and customer satisfaction. 

Package Level Debug and Fault Isolation 
Time-domain reflectometry, thermal and magnetic field imaging, and X-ray tomography are critical methods covered for non-destructively debugging and isolating failures in single and multi-chip and multi-layer VLSI packages. 

Die Level Debug and Fault Isolation Overview
A summary of electrical and physical techniques is presented as a precursor to understanding and solidifying the need for a proactive approach. Electrical test and deterministic diagnostic techniques are covered including memory bit-mapping, scan-based logic analysis, IDDq testing, and analog circuit analysis. Physical methods using photonic, magnetic, thermal, and X-ray imaging and related infrastructure are briefly discussed as both complement and supplement to the electrical methods. Finally, the entire process, dependencies, and limitations are detailed before understanding the major steps in greater depth.

Electrical Diagnostic Techniques 
Capabilities of deterministic scan-based diagnosis and bitmap approaches are examined as mainstream methods for isolating problems in logic and memory devices, respectively. IDDq and analog circuit analysis are also introduced as less rigorous but nonetheless critical diagnostic solutions. Resolution and accuracy limitations are explored in the context subsequent technical and business impacts.

Thursday 

Package and Test Preparation for Physical Fault Isolation 
VLSI packaging is rapidly increasing in density - what used to be a simple means of interconnect to the outside world has become a complex device of its own. Preparing a packaged chip for non-destructive debug and fault isolation requires numerous techniques preserving functionality and form-factor as much as possible while retaining heat dissipating ability and allowing access to internal nodes and films. Laser ablation, milling, surface grinding and micromachining methods are examined along with test fixturing. 

Physical Fault Isolation Principles
Electrical fault isolation techniques are by nature limited in spatial resolution 
to the area energized - a logic node or a memory cell for example. For many nanoscale defects and subtle non-visual defects this level of isolation is insufficient. Often electrical debug capability is limited or not available at all. Physical fault isolation uses physical effects of faulty devices and circuits, materials, and interconnects to provide spatial domain images of photonic, thermal, and magnetic field interaction that aid in pinpointing problematic regions.

Properties such as photocarrier absorption, magnetic field density, local temperature gradient, and electroluminescence are used with electrical test and high-resolution microscopy to image and characterize the operation of functioning devices and defective circuits. Methods include laser scanning microscopy, magnetic field imaging, photon emission microscopy (PEM), passive voltage contrast (PVC), and optical and electron beam induced current (OBIC/EBIC) imaging. 

Proactive Approach to Successful Debug
Planning, communication, and interaction between stakeholders are important in ensuring success when problems arise. Class material will be reviewed and synthesized into a process for ensuring the best possible plan for debug and fault isolation.

Future Challenges
Recurring design and material changes in IC technology are constantly challenging the techniques described. A brief outlook of major debug and fault isolation obstacles is offered with likely impacts assessed and necessary research paths outlined.

Regular Course Fee: EUR 1310

Early Registration Course Fee: EUR 1180
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches etc.) paid on your behalf to the course venue. 
Accommodation is not included.