Course #85

Phase Locked Loops for Wireless Communication Systems

April 19-22, 2010. Barcelona, Spain
November 22-25, 2010. Barcelona, Spain

INSTRUCTORS
Dr  Lutz Konstroffer, RF Consult GmbH, Irschenberg, Germany
Bernd Scheffler, Texas Instruments, USA

TECHNOLOGY FOCUS 
Phase Locked Loop frequency synthesizers are key buildingblocks in wireless communication systems. Good knowledge of its potential and the constraints of PLLs are important for circuit system but also design engineers. In the past, discussions on synthesizers have been centred on performance optimisation and concept partitioning. Today, the industry is making huge progress towards total integration into one piece of silicon together with other building-blocks needed for a complete radio, all with the goal to make future wireless products affordable and comfortable in use. This general trend is supported by usage of various, more digital synthesizer techniques introduced into measurement equipment 15 years ago to increase performance. 

COURSE OBJECTIVES 
This course enables engineers to understand the principles of PLL circuits and its applications and to design PLL synthesizers optimized for a given application. It introduces advanced technologies of frequency synthesis used in modern communication devices. 

Monday – LUTZ KONSTROFFER 

CONTROL LOOP BASICS 
Control loop basics are the foundation of any detailed PLL consideration. The concepts of open and closed loop gain, phase and amplitude margin and their link to the dynamical behavior are introduced. The Z-transformation as a method to describe and optimize the behavior of time discrete control loops is explained. 

• Open and Closed Loop Gain and Phase Transfer Function 
• Bode Plot, Phase Margin, Amplitude Margin
• Poles and Zeros, Characteristic Function
• Closed Loop Transfer Function, 3dBBandwith, Dynamic Control Behavior
• Describing Time Discrete Control Loops by Z-Transformation
• Principals of Modulators

Phase Noise in a Wireless System 
Parameters that describe the phase fluctuations and establish relationships 
between different sets of parameters are introduced. The impact of the noise behavior of a PLL on the receiver and transmitter performance in a wireless system is discussed. 

• The Phase Angle as a Random Process
• Parameters Describing Phase Fluctuations and Relations between Them
• SSB Phase Noise, Phase and Frequency Error 
• Effect of the Phase Noise on the Blocking and Adjacent Channel Power Performance 

PLL Components 
We focus on the components that build a PLL. All building blocks of a PLL are described in terms of their linear transfer functions. 

• VCOs
• Phase Noise in VCOs
• Phase Detector Types
• Charge Pumps 
• Use of Op-Amps
• Dividers and Mixers in a PLL 

Tuesday – LUTZ KONSTROFFER 

PLL FUNDAMENTALS 
Based on the linear description of the building blocks, we will derive the transfer functions of a PLL and their implications on the system performance such as switching time and spurious suppression. A discussion of the noise behavior of the PLL will complete this section. 

The Phase Transfer Function 

Transfer Functions for Noise and Spurious Signals 

Lock Time, Natural Frequency, Damping Factor, and Phase Margin 

2nd-, 3rd-, and High-order Filters

Correlation between Phase Comparison Frequency and Loop Bandwidth 
Requirement 

Phase and Frequency Modulation in a PLL

Sources of Phase Noise in a PLL and Its Simulation 

The Integer N PLL in a Wireless IC 

As the loop filter is a key element in any PLL, its dimensioning is based on lock time and spurious requirements. 

Loop Filter Dimensioning from Lock Time Requirements

Compromise between Spurs, Noise and Lock Time

Sources of PFD Spurs 

Charge Pump Issues

Problems Linked to Speed-up Circuits 

The Fractional N PLL in a Wireless IC 
An approach to overcome the constraints of lock time, phase noise, and spurious suppression is the fractional N concept. 

• Basics of Operation 
• Spurs Due to the Fractional Concept
•  Analog and Digital Fractional Compensation 
• Limits of Fractional Compensation Circuits 
• The Impact of Phase Detector Linearity 
• The Measurement of PLL Parameters 
• Phase Noise Measurement with a Spectrum Analyzer
• Phase Noise Measurement by Down Conversion
• Delayed Self Homodyne Phase Noise Measurement 
• Simple and High Precision Lock Time Measurement Methods 
• Measuring the PLL Phase Transfer Function 

Wednesday – BERND SCHEFFLER 

SYNTHESIZER CONCEPTS 
We review various transceiver/synthesizer concepts. Special focus is on how to modulate a carrier for TX and maximize reuse HW for RX 
in half-duplex systems. 

• On-channel Modulation
• Offset-loop 
• Open-loop Modulation
• Closed-loop Modulation 

Direct Digital Synthesis 
The architecture of a DDS is analyzed in detail. The noise and spurious response of the system is considered for each building-block. Other system parameters like lock-time and frequency resolution will be touched.

• Accumulators 
• Phase and Amplitude Quantization 
• Frequency Resolution 
• Spurious Analysis
• DAC 

Sigma-Delta PLL 
Starting from a classical PLL, the mathematical description of the noise behavior of a Sigma-Delta PLL with multi-modulus divider is developed. 
The digital fractional spurious compensation is modelled, and in a second step we perform a quantization noise simulation and extract a rule of thumb for practical usage. Frequency resolution and other key parameters are treated before advantages are summarized. 

• Sigma-Delta Modulator
• MASH
• Divider Control
• Quantization Noise
• SSB Phase Noise
• Frequency Resolution 

Thursday – BERND SCHEFFLER 

Generate Modulated Signals with digital PLLs 
The advantage of this PLL architecture to generate phase- and frequency 
modulated signals is presented. For vector modulated signals the sigma-rho concept is compared to a classical on-channel modulation concept.

• In-Band and 2-Point Modulation
• Modulation Bandwidth 
• Sigma-Rho Modulation 
• Vector Modulation
• Impairments 
• IQ Modulator
• On-Channel Modulation 

Complete Digital PLL – Digital Controlled Oscillator (DCO) 
Silicon technology trends allow new PLL architectures and increase its digital content. Starting point is the analysis of a DCO and basics of a non-linear control loop. Means to increase the frequency resolution and quantization noise will be treated on architectural level before discussing the benefits

• DCO
• Digital Loop Filter 
• All Digital Loop 
• Quantization
• Non-linear Control Loop 

Regular Course Fee: EUR 2490

Early Registration Course Fee: EUR 2240
This applies to firm registrations received 2 months before course start. 

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches etc.) paid on your behalf to the course venue. Accommodation is not included.

Payment should be made before course start.