Course #95

Cupper-Low k Interconnect Technology: 

Processing and Reliability of Cu Low k Interconnect Metallization

October 20-22, 2010. Dresden, Germany

(See also course #75, a 2.5 day course, which is conveniently scheduled before this course)

INSTRUCTORS
Dr Jeffrey Gambino, IBM Microelectronics, Essex Junction, Vermont, USA
Professor Dr. Ehrenfried Zschech, Fraunhofer Institute for Non-Destructive Testing, Dresden, Germany

TECHNOLOGY FOCUS 
With continuing device scaling and on-chip interconnect dimensions below 100nm, wiring interconnect becomes increasingly important in limiting chip density, performance and reliability. Fundamental changes in interconnect materials are needed with Cu replacing Al and low-permittivity dielectrics replacing SiO2.The integration of these two advanced materials results in significant reduction in signal delay, cross-talk, and power dissipation, enabling the semiconductor industry to continue device scaling. 

The fabrication of Cu/low-k interconnect stacks requires novel materials and processes, including electroplating Cu, dual damascene structures, chemical-mechanical polishing, ultra-thin barriers, and passivation layers. These novel materials and processes give rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low-k interconnect systems. 

As the technology continues to advance, the implementation of porous low-k dielectrics beyond the 45 nm node will bring in new processing and reliability issues, such as pore sealing, etch damage and ultra-thin barriers. These problems will be discussed together with recent advances in material and process development and reliability improvement for Cu/low-k interconnect systems. 

COURSE CONTENT 
This course will provide an overview of the materials, processes, and reliability for Cu/low-k interconnect stacks. It will focus on basic issues relating to copper deposition, damascene structure and processing, and on low k dielectric materials, their processing and reliability issues like electromigration, stress-induced voiding and mechanical weakness in case of low-k and ultra low-k materials. 

Wednesday pm – JEFFREY GAMBINO

PROCESS INTEGRATION
In this section we focus on process integration, including dielectric deposition, patterning, metal deposition, and CMO. We will also discuss basic packaging processes.

PROCESSING OF COPPER LOW-K INTERCONNECT STRUCTURES 

Dielectric Deposition 

• Dielectric Selection
• Spin on Processes 
• CVD Deposition
• Post Deposition Processing 
• Solvent Removal, Porogen Removal, Curing 
• Characterization of Deposited Films 
• Porosity, Thickness, Composition, Bonding 

Dielectric Etching 

• Via First vs. Line First Dual Damascene Schemes
• Hardmask vs. Softmask Processes 
• Resist Poisoning 
• Etch Control 
• Resist Erosion, Line-edge Roughness, Profile Control 
• Impact of Etch Processes on Dielectrics 
• Lateral Etching, Low-k Oxidation
• Hybrid Structures 

Liner Deposition 

• Liner Selection
• Precleans and Damage Removal 
• Wet Cleans 
• In-situ Cleans
• Metal Deposition Options 
• PVD Processes
• ALD Processes 
• Resistance Impact and Liner 
• Thickness Uniformity and Control 
• Pore Sealing 

Thursday am - JEFFREY GAMBINO

COPPER DEPOSITION AND CHEMICAL MECHANICAL POLISHING 

Copper Deposition 

• Deposition Options
• Deposition Seeding
• PVD
• Alternative Seed Processes
• ALD, CVD, Electroless Plating 
• Copper Electroplating 
• Role of Additives
• Super Filling of High Aspect Ratio Structures 
• Post Annealing and Line Resistance Control
• Electroless Deposition of Refractory Metals 

CMP, Chemical Mechanical Polishing 

• Damascene Processing
• CMP Slurries
• CMP Pads
• CMP Process Problems
• Erosion, Dishing, Corrosion, Scratches, Residues 
• Alternative Planarization Processes
• Electropolishing, E-CMP 
• Effect of CMP on Low-k Dielectrics
• Post-CMP Cleaning 

Packaging Processes 

• Dicing
• Wirebond Process 
• Flip Chip Process 

Dielectric Breakdown and Leakage Current Characteristics 

Thursday pm - EHRENFRIED ZSCHECH 

COPPER METALLIZATION AND LOW-K DIELECTRICS 

We begin with an overview of interconnect scaling trends, problems, and potential solutions. We then provide a detailed discussion on current developments and processing integration of low-k dielectrics. Key areas discussed include chemical bond and electron polarizability and how they are optimized to yield desired properties for low-k dielectrics. Discussions on process integration include deposition and etching of low k dielectrics and the formation of ultra-thin liners in damascene structures. The impact of key process steps on performance and reliability of the final product will be highlighted and discussed. 

Copper Interconnect Technology 

• Interconnect Scaling Trends 
• Performance and Density Limitations 
• Wiring Design of Cu Interconnects
• Need for Advanced Materials 
• Cu Damascene Interconnect Structures 

Development of Low-k Materials 

• Dielectric and BEOL Roadmap
• Dielectric Constant and Chemical Bond
• Molecular Design of Low-k Dielectrics 
• Fully Dense and Porous Low-k Dielectrics 

Friday - EHRENFRIED ZSCHECH 

RELIABILITY 

We will now focus on reliability issues of Cu damascene structures. This will include electromigration, stress-induced voiding, leakage current characteristics and the discussion of mechanical weakness. Recent advances in improving Cu/low-k reliability will be discussed, including the use of metal coatings to improve adhesion and electromigration performance. Packaging effects on reliability of products with Cu/low-k interconenct stacks (Chip-package interaction) will be an additional topic.. 

Structural Integrity and Reliability of Cu/low-k interconnect Stacks 

• Reliability-limiting Processes, Materials and Structures 
• Statistical Approaches and Analytical Techniques to Describe Reliability and to Study Degradation Mechanisms
• Electromigration: Degradation mechanisms, process and materials effects
• Stress Induced Void Formation in Cu/low-k Interconnect Stacks 
• Leakage Current in Cu/low-k interconnect Stacks
• Mechanical Weakness of Low-k and Ultra Low-k Materials, Concepts to Overcome this Drawback
• Chip-package Interaction and Impact on Cu/Low-k Reliability
• 3D Integration - a New Challenge 

Regular Course Fee: EUR 1915

Early Registration Course Fee: EUR 1720
This applies to firm registrations received 2 months before course start. 

Combination of courses #75 and #95: EUR 2995 (Early Registration: EUR 2725)

University Student and Faculty Rate:
Two university participants are welcome to attend for one course fee if payment is to be made from university funds.

Deliverables:
The course fee covers tuition, course material, and the day conference packages (morning/afternoon refreshments, lunches etc.) paid on your behalf to the course venue. 
Accommodation is not included.