Chip Interconnection Technology and Process Integration

TECHNOLOGY FOCUS
With continuing device scaling, wiring interconnect becomes increasingly important in limiting chip density and performance. The evolution of the interconnect technology brings forth new and increasingly stringent materials and processing requirements. The driving forces that dictate the materials and processing requirements of metallization systems for high density circuits will be examined, emphasizing the current approaches used for Al-based and Cu-based interconnect development. As the device technology continues to advance, the interconnect development presents significant challenges for materials, process integration and reliability. Discussions will include interconnect development for specific applications, such as power devices and automotive modules.

COURSE CONTENT
This course provides an overview of on-chip interconnect technology with emphasis on Al-based metallization systems and the evolution to Cu-based metallization will also be discussed. First, the technology trend of interconnect development for integrated circuits will be identified and examined. The trade-off between density and performance with scaling will be discussed. Then key areas in materials and processes for interconnect metallization systems will be reviewed, including contact metallurgy, dielectric materials, barriers and contacts, and damascene processes. This will include interconnect systems development for special applications, such as power devices and automotive modules. Materials requirements, deposition, processing and characterization of thin films and interconnect structures will be reviewed.  Electromigration and stress voiding reliability will be discussed, focusing on the effects due to interconnect scaling, materials and structure changes.

WHO SHOULD ATTEND
This course is intended for individuals who wish to expand their knowledge in the materials, processing and reliability aspects of ULSI metallization systems. The subjects covered in this course extend from fundamentals of deposition and processing of metal and dielectric films and structures to the current technology of Cu/low-k interconnects. 

Monday - PAUL HO
Trends in Interconnect Technology
The scaling of VLSI and ULSI circuits and the impact on the performance and density of interconnects will be reviewed. Past and future trends in interconnect development and technology roadmap will be presented. 
Key issues for controlling interconnect density and performance will be examined, including effects of device scaling and wiring optimization. New interconnects with copper and low dielectric constant material and 3D stack structures will be introduced.

Contact Metallization
The basic requirements for metallization systems in device contacts and interconnect structures will be examined. Key aspects of contact metallization will be discussed, including formation of Schottky and ohmic contacts, interfacial reactions, self-aligned silicidation processes and contact reliability. Materials and processing issues for future contact metallization will be discussed addressing the effect of device scaling and deep submicron technology. 

Thermal Stresses in Thin Films and Line Structures
The characteristics of thermal stresses in thin film and line structures will be discussed. The dielectric confinement leads to a triaxial stress state in line structures with distinct characteristics in contrast to the biaxial stress state in thin films. The stress states in line structures and 3D through-silicon vias will be compared. The stress effect  on the deformation mechanism and interconnect reliability will be examined, emphasizing on interfacial delamination in interconnect structures and 3D through-silicon vias.

Tuesday - MARTIN GALL
Thermal and Mechanical Properties of Thin Films
Thermodynamics and kinetic aspects of thin film deposition will be reviewed. The relationship between microstructure, deposition processes and stresses in thin films will be presented. The effects of annealing, encapsulation, and alloying will be described. Examples will be taken from multilevel interconnections.

Thin Film Deposition and Control of Film Properties
Thin film deposition processes will be presented with emphasis on physical deposition methods. Evaporation, Sputtering and Chemical Vapour Deposition (CVD) of metals, alloys, and compounds will be described with examples taken from silicon technology. The relationship between thin film properties and deposition processes will be presented. The effects of ion bombardment, temperature, and reactive gases on the composition and microstructure of thin films will be described. Case studies will be used to illustrate the techniques for controlling film properties. 

Processing of Advanced Multilayered Structures
Multilayered interconnect structures designed to achieve high density and high performance will be discussed. Processing issues for Al metallization will be compared with Cu metallization, projecting the challenges for future technologies. Planarization processes using the damascene structure and chemical mechanical polishing will be reviewed. Barrier layers and deep trench filling for submicron interconnects will be described. 

Interconnects for Specific Device Applications
Interconnect schemes for specific device applications such as power devices and automotive modules will be discussed. Due to different device requirements such as high power consumption or elevated temperature usage, interconnect structures have to be tailored towards their specific needs. An overview of the various device types will be given and their impact on the choice of interconnect scheme will be discussed. 

Wednesday am- MARTIN GALL
Metallization Reliability
Major reliability issues for multilevel submicron interconnects will be discussed, focusing on electromigration and stress-induced void formation.  Electromigration characteristics for Al and Cu interconnects will be compared, including damage formation mechanisms and effects due to interconnect materials and damascene structures. The statistical approach for early failure detection in high-density interconnect systems will be presented. Stress-induced void formation will be discussed, emphasizing thermal stress behaviour in confined line structures, stress measurement of interconnect structures, and analysis of stress voiding reliability. 

Said about the course from previous participants:
"Possibility to ask and discuss with the teachers; to hear not only from newest technology point of view - also for older technology the information will be useful."
"Both lecturers were easily approached about our specific defect mechanisms and problems in house."




See also course #95 Copper Low-k Interconnect Technology- Processing and Reliability of Cu Low-k Interconnect Metallization, a 2.5 day course, conveniently scheduled after this course.