Plasma Etching for CMOS Technology and ULSI Applications

TECHNOLOGY FOCUS 
Extensive efforts to miniaturize semiconductor devices is largely attributed to lithography and etching technologies that allow semiconductor thin films patterning in the range of dimensions determined by the semiconductor road map. During more than 30 years, classical materials, such as aluminum, SiO2, and poly-silicon, have been integrated in semiconductor devices. 

Nowadays, the technology imposes to work with new materials at each technological node. The integration of new high k and low k dielectric materials, metals at the front and back end of device fabrication, bring on new problem categories. This imposes the necessity to quickly build up expertise at a rate unprecedented in all the history of semiconductor manufacturing. 

COURSE CONTENT AND OBJECTIVES 
This course is intended to provide an understanding of plasma processes for CMOS applications and ULSI technology. We will discuss fundamental and practical aspects of front end and back end plasma processes for deep submicron CMOS logic processes. 
The course is based on experimental results obtained using commercial etchers connected to very powerful diagnostics of the plasma and the plasma surface interaction. The discussions cover several aspects of etch processes of materials integrated in advanced CMOS devices, etch mechanisms, and situations that may be encountered for some important plasma processes. 

Fundamental parameters obtained from advanced characterizations are used to discuss and analyze plasma etch processes. The emphasis is on real problems, fundamental understanding of processes used in manufacturing, considerations for integration with other steps, and issues brought by the fast device scaling. 
Processes covered in detail include silicon gate patterning and all the problems related to critical dimension control as well as results on metal gate and high k dielectric etching. The etch processes associated with the integration of low k materials will be extensively discussed. 

Wednesday 
Fundamentals in Plasma Processing

• Ion Neutral/Synergy
• Impact of Neutral Flux to Ion Flux Ratio on Plasma Processes
• Etch Anisotropy
• Passivation Layer Formation in Plasma Processes
• Temperature Effects in Plasma Etching
• Microscopic Uniformity in Plasma Etching
• Impact of Aspect Ratio on Etching Processes
• Charging Effects in Plasma Etching
• Impact of Reactor Wall on Plasma Processing
• Micro-Trenching Formation
• Etch Mechanism of Silicon in Halogen Based Plasmas
• SiO₂ Etch Mechanisms
• Polymer Etching for Microelectronics Applications

Thursday
Silicon, Metal and High K Etching Processes for CMOS Applications

• Thin Gate Oxide Behavior during Gate Etch Processes
• Silicon Recess during Gate Etch Processes
• Impact of Plasma Processes on 193 Nm Resists
• Hard Mask Opening Processes
• Silicon Gate Etching in Inductively Coupled Plasmas: Hbr/Cl₂/O₂, Hbr/Cl₂/O₂/CF₄, SF₆/CH₂F₂ Chemistries
• Metal Gate Etching
• The Etch Challenges of High K Materials
• Chamber Wall Coating during Si/Metal/High K Etching
• Chamber Wall Cleaning Strategies for CMOS Applications

Oxide and Low k Etching

• Fundamentals in SiO₂ Etching
• Low k Materials in Advanced Interconnects

Friday
Oxide and Low k Etching (Cont'd)

• Mechanisms of Low k Polymer Etching in Medium Density and High Density Plasmas
• Etch Mechanisms of SiOC-based Materials
• Selectivity Issues
• Fluorocarbon Film Thickness Measurement by XPS
• The Impact of Porosity on Etching Mechanisms of SiOC-based Materials
• Dual Hard Mask Strategies
• Impact of Ashing Plasmas and Chemistries on Low k Material Modifications

Said about the course from previous participants:
"Good topics, well defined and built up."
"Good explanations for daily problems I face in my work."
"Excellently compiled topics with structure."
"Summaries of difficult topics, really new topics are introduced."
"Strong updating about new techniques."




See also course #87 Plasma-Assisted Etching and Reactive Ion Etching Using High and Low Density Plasmas