Course Calendar - CEI-Europe
Course #53

Mastering Power Integrity with Signal Integrity and EMC Foundations

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

Have you attended this course? Click the button below to update your LinkedIn profile.

LinkedIn Add to Profile button

 

TECHNOLOGY FOCUS
Power integrity,PI, has emerged as the latest and still growing challenge for electronic designs, as the landscape for the three disciplines  Signal Integrity, Power Integrity and Electromagnetic Compatibility has shifted. While signal integrity, SI, and electromagnetic compatibility, EMC, still pose challenges, their disciplines and the possible pitfalls and their solutions have been more widely studied and understood.  Power noise, and its impact on SI and EMC, on the other hand, creates daily new challenges and their solutions are still being worked out. Whether it is component characterization or high-speed channel link budgeting, the power integrity tasks can not be successfully solved without taking into account the signal integrity and EMC principles.

COURSE FOCUS
This unique course focuses on PI with a broad and unified outlook to SI and EMC. It shows that not only the underlying physics, but also many design rules are essentially the same across these disciplines and the seemingly contradictory rules are the result of different initial conditions.  
The course is based on fourty years of teaching, research and successful industrial design experience.  It shows working and proven design practices and pitfalls to avoid.  It will illustrate live HW and SW demonstrations, ranging from a variety of home-made tools to professional commercial HW and SW.
This course is a must for system board and package designers, power engineers and their managers as well as for silicon designers who want to understand the application environment of their chips.

COURSE CONTENT
This unique course provides a unified analysis and design approach to the power-integrity, signal-integrity and electromagnetic compatibility disciplines with the main focus on power distribution network design, validation, testing and simulations. It emphesizes the most recent challenges that the digital and mixed analog/digital designers face, with time devoted to signal integrity analysis, design methods, solutions and component selection.
We will deal with the underlying physical rules with minimal mathematics. With interactive software and live hardware and software demo illustrations, the various good and bad design choices are explained and trade-offs are shown for achieving high-performance yet cost-effective designs.
Among others, the course shows why PI requires the impedance, whereas SI requires scattering parameters for their designs and validation processes.  Participants will learn how bit error rate (BER) and jitter depends on power noise, how to analyze and minimize their effects. You will also learn the surprising fact that conductor surface roughness is actually more detrimental for low-frequency power distribution than for high-speed signaling. We also show the counter-intuitive fact that current distribution in conductors is not uniform even at DC, resulting in geometry-dependent extra losses.

The course provides an overview of power distribution design methodologies and shows that worst-case power noise and worst-case high-speed eye closure can be calculated based on the same principles. Cost-effective PCB stackup, material and component choices are discussed together with simulation and measurement solutions for power distribution networks and high-speed signaling. The course also shows how to select, characterize and measure DC-DC converters and power filters.
Participants will receive several of the tools and simulation files shown in the class as well as the book Power Distribution Design Methodologies. There is an option to purchase the book Frequency-Domain Characterization of Power Distribution Networks at a special discount, available only to course participants.

DAILY SCHEDULE

This course will mostly discuss power integrity, but with emphasized and specific outlooks to signal integrity and EMC.
A series of dedicated hardware (HW) and software (SW) illustrations and design examples will show and explain the underlying physical phenomena and major design rules of proper design.

MONDAY
Common Foundation of Power Integrity, Signal Integrity and EMC

  • How signal spectrum is related to PI, SI and EMC requirements?
  • When do you need time or frequency-domain solutions?
  • Commonalites and differences between power planes and signal traces
  • Characteristic impedance, delay, matching and termination solutions and rules
  • Understanding impedance and scattering matrices for PI and SI use
  • Parasitics of RLC components, how to interpret catalog data and how to create      accurate simulation models for power and signal integrity

Examples, live HW and SW demos: Calculation of interconnect parameters, reflection, matching, signal bandwidth and spectra

TUESDAY
Multi-Line, Loaded and Lossy Interconnects

  • Printed circuit board construction rules, laminate selection; how material properties impact PI, SI and EMC
  • The various types of crosstalk in power and signal networks
  • Crosstalk reduction, crosstalk metrics in time and frequency domain
  • Differential Interconnects, effects of imbalance, interpreting and calculating mixed-mode S parameters and mode conversion
  • Effect of electrical loading and discontinuities on power planes and signal traces
  • Designing for multi-rail power distribution and multi-line signal crosstalk, simultaneous switching noise
  • DC drop on planes, DC power distribution, minimizing voltage drop by proper connections

Examples, live HW and SW demos: Effect of capacitive loading on power planes and transmission bandwidth, designing for a specific crosstalk goal

WEDNESDAY
System Design

  • When do we need single-point or multi-point grounding?
  • Grounding options in mixed-mode applications
  • Shielding and electromagnetic interference rules and solutions
  • Skin loss, dielectric loss, surface roughness, laminate and copper selection, through holes and blind/buried Vias, bends, stubs
  • Clock distribution, skew, jitter, jitter separation, relation to bit error rate (BER) and power noise
  • Clock sources and drivers, clock PLLs, spread-spectrum Clocking in signaling and power distribution
  • Jitter tolerance and jitter transfer
  • Inter symbol interference in power and signal integrity, Reverse Pulse Technique and Peak Distortion Analysis; linear network solutions of passive interconnects

Examples, live HW and SW demos: Termination and resonances in power planes and Clock networks

THURSDAY
Power Distribution Design Methodologies

  • DC-DC converters, transient response, output impedance, loop stability
  • Lumped PDN Design, the Target Impedance concepts and its proper use
  • Synthesizing PDN impedance: pros and cons of multi-pole, big-V and other            design strategies
  • Bypass capacitor selection and placement, service area of capacitors
  • Connecting the charge time-of-flight and target-impedance concepts
  • Multi-node PDN Design
  • Proper design of power filters

Examples, live HW and SW demos: Simulation of bypass capacitor service area, output impedance and gain-phase plots of DC-DC converters

FRIDAY
Signal and Power Integrity Measurements and Modelling

  • Creating simulation models for DC-DC converters, bypass components, high-speed interconnects
  • Simulating vias, planes, bypass capacitors, DC-DC converter stability and output impedance
  • Major challenges and their solutions in power and signal-integrity                measurements

Examples, live HW and SW demos: Measuring very low impedances reliably and accurately, filter design and performance

 

EMC-Novak2

 
Length: 5 days
Regular Course Fee: 3250 euro
Early Course Fee: 2925 euro
CEI-Europe's Newsletter

CEI-Europe AB, Teknikringen 1F, SE-583 30 Linköping, Sweden Phone +46-13-100 730 Fax +46-13-100 731 cei@cei.se