Course Calendar - CEI-Europe
Course #36

Silicon Device Technology: Materials and Processing Overview

The course date and layout for October 2017 is changed from a previous 5-day course into a 4 day course Monday-Thursday October 9-12, 2017 in Dresden.     (See outline in red below). All four course days will be taught by Dr. Jeffrey Gambino.

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

TECHNOLOGY FOCUS

The rapid growth of the semiconductor industry has relied on the continual evolution of materials and processing compatible with fabricating modern silicon-based integrated circuits. Continuous feature scaling has led to increased integration, lower cost, higher speed, and compactness, however, the challenges of fabricating smaller feature sizes has demanded advances in materials processing.  More recent demands include lower energy consumption and expanded functionality. Advances include strain engineering with Ge alloying, Silicon-on-Insulator (SOI), penetration of Cu metallization and required barrier materials, and development of high κ dielectrics.

COURSE CONTENT
This course will provide an overview of the entire fabrication process. It will include all the key materials involved and the process areas utilized in device manufacturing. This course is thus addressed to a broad audience and is not intended as a research review, although it will be taught at a high level and in many areas will require familiarity with the subject matter.

Monday 
Si Front-end Manufacturing 
An overview of the entire front-end manufacturing process will be presented. A perspective on process bottlenecks and future 
trends, as outlined in the most recent (2010) 'International Technology 
Roadmap for Semiconductors', is presented.

  • Si Wafer Production
  • Epitaxy
  • Oxidation
  • Dielectric Deposition
  • Ion Implantation
  • Metallization
  • Lithography
  • Etching

Device Technologies and Semiconductor Materials 
The basic device technologies will be discussed, including bipolar and CMOS.

  • Electrical, Optical, and Structural Properties of Silicon
  • Control of the Point and Extended Defect Densities
  • Origin of Defects and Their Influence on Device Performance
  • IC Materials Characterization for Process Improvement and Achieving High Yield

Process Induced Defects and Device Performance 
Common impurities introduced during materials growth and their influence will be discussed. The crystallography of the diamond structures and the formation mechanisms and structures of extended defects, i.e. stacking faults, misfit dislocations, twins, will be reviewed. Both intrinsic and extrinsic gettering technologies will be described with a discussion of their effects on subsequent device processing and device parameters.

Large Diameter Wafers
It is essential to have the highest quality Si wafers to achieve high process yields. The wafering process and issues related to quality assurance and acceptance will be addressed, along with recent developments in deployment of the 450 mm wafer.


SOI, Wafer Bonding, SiGe and Other Emerging Technologies 
Several technologies are emerging to meet the demands for higher speed, higher density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology using various approaches, is now commercially available. Promises and limitations of SOI will be presented to ease the decisions in wafer specification. 

The SixGe1-x alloy is another advanced material that is currently emerging into the marketplace. These alloys allow the properties of Si to be engineered through composition control. Applications include intrinsic gettering through strain field control and high-speed devices. The impact of the growth process on the properties and an overview of the device applications will be presented. 

Silicon Epitaxy by CVD
Silicon epitaxial deposition is a strategic process technology in large volume manufacturing. The understanding and control of this technology is critical to the success of the production of high quality devices and circuits.  Topics to be covered include:

  • Substrate Crystal Orientation, Deposition Parameters, and Choice of Silicon Source Material
  • CVD Fundamentals for Si Deposition Chemistries
  • The Influence of Deposition Parameters on Film Quality
  • Procedures to Prepare Wafers for Epitaxy
  • Film Quality and Device Performance
  • Si Etching by Wet Processes
  • Isotropic and Anisotropic Etchants

Tuesday
Silicon Oxidation
The role of the native oxide of Si as an enabler of advanced Si technology cannot be overstated. This section outlines the fundamental aspects of silicon oxidation.

  • Gate Oxide, Surface Passivation, Mask, Device Isolation
  • Growth Models for Wet and Dry Oxidation
  • Surface Preparation
  • Charge and Atom Transport
  • Dopant Redistribution
  • Orientation Effects
  • Properties of Ultra-thin Oxides
  • Novel Processes such as Rapid Thermal Oxidation

Deposition of Metals and Dielectrics by Physical and Chemical Methods
The various physical and chemical approaches to the deposition of metal and dielectric materials are outlined and compared. The 'Roadmap' predicts that Atomic Layer Deposition (ALD) methods will eventually become the dominant 
process because it is well suited for deposition of ultra-thin, highly conformal films over small device features.

Integrated Circuit Metallization Systems

  • The scaling of VLSI and ULSI circuits and the impact on the performance and density of interconnects will be reviewed. Current interconnects with Cu and low k dielectrics and recent development on 3D interconnects will be discussed. Multilayered Interconnect Structures: High density and high performance
  • Scaling and Wiring Requirements of ULSI Circuits
  • Interconnect Performance and Density
  • Requirements for Metallization Systems in Device Contacts and Interconnecting Lines
  • Major Factors Affecting Reliability of Multilayered Sub-micron Interconnects
  • Current  Interconnects with Cu and Low k Dielectrics
  • Recent development on 3D interconnects

Dielectrics for Multilayered Metallization
Dielectric materials play an important role in controlling the performance and density of interconnect structures. The material requirements, processing and effect on reliability of the dielectrics will be discussed.

  • Thin Film Dielectrics
  • The Evolution of Interlevel Dielectrics from SiO2 to Low k Dielectrics
  • Material Requirements and Integration Issues
  • Development of Organic and Inorganic Low k Materials
  • Tradeoff of Thermo-Mechanical Properties
  • Impacts on Reliability

Wednesday
CMP for Microelectronics Applications 
Chemical Mechanical Planarization (CMP) is an enabling technology for the microelectronics industry. The empirical nature of CMP and how it bridges many engineering disciplines for resolution of its numerous challenges will 
be emphasized.

  • How to Effectively Utilize CMP
  • Evolution and Revolution of CMP Equipment and Consumables
  • Characterization Techniques for Process Development and Control
  • Advantages and Limitations of CMP Processes for
  • Advanced Microelectronics Applications

High k Dielectric Materials 
Alternate gate dielectric materials are being developed, as the continuously reduced SiO2 thickness is approaching its physical limitation and direct electron tunneling results in unacceptably high leakage currents.

  • Potential High k Materials Ranging from 10 to 100: Transition metal oxides, ferroelectric materials, metal silicates
  • The Impact of Thin Gate Oxides on Device Performance
  • Benefits of the Use of High k Dielectrics
  • Material Properties, Growth Methods, and Impact on Device Performance


Ion Implantation and Diffusion
Critical issues of ion implantation and junction formation in silicon devices are discussed.

  • Process Issues in Applying Ion Implantation/Annealing
  • Materials Issues of Ion Penetration, Damage Production, and Masking
  • Annealing Implanted Layers in Silicon: Oxidation over implanted layers, furnace annealing, Rapid Thermal Processing (RTP)
  • Critical Issues for Creating pn Junctions in Silicon: Low leakage junctions, removing damage, controlling diffusion during the annealing of implantation damage, scaling of pn junction depths, contacting, diffusion through thin oxides in doped polysilicon gate/oxide/ silicon devices
  • Process Simulation for Design and Control of Implanted and Annealed Junctions

Thursday
Reliability and Yield
The success of an IC manufacturing facility is directly connected to IC reliability and product yield. An overview of failure mechanisms and yield limitations will be presented. The discussion will include approaches to circuit and layout design, device design, materials selection, process optimization, as well as thermo-mechanical considerations. Proven yield improvement management processes will be outlined.

 

*******

Course outline for 2016.

Monday - TIM ANDERSSON
Si Front-end Manufacturing 
An overview of the entire front-end manufacturing process will be presented. A perspective on process bottlenecks and future 
trends, as outlined in the most recent (2010) 'International Technology 
Roadmap for Semiconductors', is presented.

  • Si Wafer Production
  • Epitaxy
  • Oxidation
  • Dielectric Deposition
  • Ion Implantation
  • Metallization
  • Lithography
  • Etching

Device Technologies and Semiconductor Materials 
The basic device technologies will be discussed, including bipolar and CMOS.

  • Electrical, Optical, and Structural Properties of Silicon
  • Control of the Point and Extended Defect Densities
  • Origin of Defects and Their Influence on Device Performance
  • IC Materials Characterization for Process Improvement and Achieving High Yield

Process Induced Defects and Device Performance 
Common impurities introduced during materials growth and their influence will be discussed. The crystallography of the diamond structures and the formation mechanisms and structures of extended defects, i.e. stacking faults, misfit dislocations, twins, will be reviewed. Both intrinsic and extrinsic gettering technologies will be described with a discussion of their effects on subsequent device processing and device parameters.

Large Diameter Wafers
It is essential to have the highest quality Si wafers to achieve high process yields. The wafering process and issues related to quality assurance and acceptance will be addressed, along with recent developments in deployment of the 450 mm wafer.


SOI, Wafer Bonding, SiGe and Other Emerging Technologies 
Several technologies are emerging to meet the demands for higher speed, higher density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology using various approaches, is now commercially available. Promises and limitations of SOI will be presented to ease the decisions in wafer specification. 

The SixGe1-x alloy is another advanced material that is currently emerging into the marketplace. These alloys allow the properties of Si to be engineered through composition control. Applications include intrinsic gettering through strain field control and high-speed devices. The impact of the growth process on the properties and an overview of the device applications will be presented. 

Silicon Epitaxy by CVD
Silicon epitaxial deposition is a strategic process technology in large volume manufacturing. The understanding and control of this technology is critical to the success of the production of high quality devices and circuits.  Topics to be covered include:

  • Substrate Crystal Orientation, Deposition Parameters, and Choice of Silicon Source Material
  • CVD Fundamentals for Si Deposition Chemistries
  • The Influence of Deposition Parameters on Film Quality
  • Procedures to Prepare Wafers for Epitaxy
  • Film Quality and Device Performance
  • Si Etching by Wet Processes
  • Isotropic and Anisotropic Etchants

Tuesday - TIM ANDERSON/JEFFREY GAMBINO
Silicon Oxidation
The role of the native oxide of Si as an enabler of advanced Si technology cannot be overstated. This section outlines the fundamental aspects of silicon oxidation.

  • Gate Oxide, Surface Passivation, Mask, Device Isolation
  • Growth Models for Wet and Dry Oxidation
  • Surface Preparation
  • Charge and Atom Transport
  • Dopant Redistribution
  • Orientation Effects
  • Properties of Ultra-thin Oxides
  • Novel Processes such as Rapid Thermal Oxidation

Deposition of Metals and Dielectrics by Physical and Chemical Methods
The various physical and chemical approaches to the deposition of metal and dielectric materials are outlined and compared. The 'Roadmap' predicts that Atomic Layer Deposition (ALD) methods will eventually become the dominant 
process because it is well suited for deposition of ultra-thin, highly conformal films over small device features.

Integrated Circuit Metallization Systems

  • The scaling of VLSI and ULSI circuits and the impact on the performance and density of interconnects will be reviewed. Current interconnects with Cu and low k dielectrics and recent development on 3D interconnects will be discussed. Multilayered Interconnect Structures: High density and high performance
  • Scaling and Wiring Requirements of ULSI Circuits
  • Interconnect Performance and Density
  • Requirements for Metallization Systems in Device Contacts and Interconnecting Lines
  • Major Factors Affecting Reliability of Multilayered Sub-micron Interconnects
  • Current  Interconnects with Cu and Low k Dielectrics
  • Recent development on 3D interconnects

Dielectrics for Multilayered Metallization
Dielectric materials play an important role in controlling the performance and density of interconnect structures. The material requiremenets, processing and effect on reliability of the dielectrics will be discussed.

  • Thin Film Dielectrics
  • The Evolution of Interlevel Dielectrics from SiO2 to Low k Dielectrics
  • Material Requirements and Integration Issues
  • Development of Organic and Inorganic Low k Materials
  • Tradeoff of Thermo-Mechanical Properties
  • Impacts on Reliability

Wednesday a.m. - TIM ANDERSON
CMP for Microelectronics Applications 
Chemical Mechanical Planarization (CMP) is an enabling technology for the microelectronics industry. The empirical nature of CMP and how it bridges many engineering disciplines for resolution of its numerous challenges will 
be emphasized.

  • How to Effectively Utilize CMP
  • Evolution and Revolution of CMP Equipment and Consumables
  • Characterization Techniques for Process Development and Control
  • Advantages and Limitations of CMP Processes for
  • Advanced Microelectronics Applications

High k Dielectric Materials 
Alternate gate dielectric materials are being developed, as the continuously reduced SiO2 thickness is approaching its physical limitation and direct electron tunneling results in unacceptably high leakage currents.

  • Potential High k Materials Ranging from 10 to 100: Transition metal oxides, ferroelectric materials, metal silicates
  • The Impact of Thin Gate Oxides on Device Performance
  • Benefits of the Use of High k Dielectrics
  • Material Properties, Growth Methods, and Impact on Device Performance

 

Wednesday p.m. - ROEL GRONHEID
Optical Lithography

The continuous trend of miniaturization in IC manufacturing and the importance of lithography as an enabling technology will be presented. 
Optical lithography has till now always been the workhorse of the industry. The lithographic process of optical lithography will be analyzed.

  • Image Formation in the Optical Lithography Process
  • Basics of the Resist Chemistry
  • Issues Encountered when Applying Resists to Real Device Processing
  • Resolution Enhancement Techniques: Phase shifting masks, off-axis illumination, optical proximity correction

Recently, 193nm immersion lithography, double patterning and 13.5nm EUV lithography have been introduced techniques for further scaling the resolution limits of optical lithography. This course will address the current status of each technology and the technological challenges for each of these new technologies and discuss the anticipated insertion points.

Thursday a.m. - GILES CUNGE
Plasma Etching and Plasma-Enhanced CVD

  • Reactive Gas Glow Discharges: Plasma etching, reactive ion etching, and PECVD
  • Operation of Low and High Density Plasma Sources
  • Surface Science Aspects of Plasma Etching
  • The Role of Energetic Ion Bombardment in Obtaining Etch Profile Anisotropy
  • Etching of Silicon and Its Compounds in Halogen-based Etching
  • PECVD and Its Role in Plasma Etching
  • PECVD Processes of Greatest Importance in Semiconductor Manufacturing

Thursday p.m. - JEFFREY GAMBINO
Ion Implantation and Diffusion

Critical issues of ion implantation and junction formation in silicon devices are discussed.

  • Process Issues in Applying Ion Implantation/Annealing
  • Materials Issues of Ion Penetration, Damage Production, and Masking
  • Annealing Implanted Layers in Silicon: Oxidation over implanted layers, furnace annealing, Rapid Thermal Processing (RTP)
  • Critical Issues for Creating pn Junctions in Silicon: Low leakage junctions, removing damage, controlling diffusion during the annealing of implantation damage, scaling of pn junction depths, contacting, diffusion through thin oxides in doped polysilicon gate/oxide/ silicon devices
  • Process Simulation for Design and Control of Implanted and Annealed Junctions

Friday - JEFFREY GAMBINO
Reliability and Yield
The success of an IC manufacturing facility is directly connected to IC reliability and product yield. An overview of failure mechanisms and yield limitations will be presented. The discussion will include approaches to circuit and layout design, device design, materials selection, process optimization, as well as thermo-mechanical considerations. Proven yield improvement management processes will be outlined.

 

citatteckenSaid about the course from previous participants:
" Information about advanced manufacturing technology."
" Video to illustrate fab work. Future process and future technology."
" Good view on new technologies - latest developments."
" The talent and strong background of the lecturers."
"Widely covered aspects, get a feeling how each discipline is working and thinking."



 
Length: 4 days
Regular Course Fee: 2695 euro
Early Course Fee: 2425 euro
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