Course Calendar - CEI-Europe
Course #88

Plasma Etching for CMOS Technology and ULSI Applications

The course date and layout for October 2017 is changed from a 3-day course Wednesday to Friday, to a 1+ 3 day course Monday-Thursday October 9-12, 2017 in Dresden. All four course days will be taught by Dr. Maxim Darnon:

#87 day 1: Plasma fundamentals
- Fundamentals of cold plasma physics
- Plasma sources used for etching application
- Plasma surface interactions involved in etching
#87 day 2 / #88 day1: Etching fundamentals
- Pattern transfer in plasma etching
- Profile control for plasma etching
- Monitoring and controlling a plasma etching processes
#88 day 2: Plasma etching for Front End Of Line application
- Photoresist and mask
- Poly silicon gate etching
- Metal gate / High-k etching
- Atomic Layer Etching
- New patterning technologies
- New transistor architectures
#88 day 3: Plasma etching for Back End Of Line application
- Etching with a fluorocarbon-based plasma
- Spacers etching
- Contacts etching
- Dense SiOCH etching for interconnects
- Porous SiOCH etching for interconnects
- High aspect ratio structures etching

MONDAY October 9, 2017

Topics from previous course #87:

PLASMA FUNDAMENTALS

- Fundamentals of cold plasma physics

- Plasma sources used for etching application

- Plasma surface interactions involved in etching

(more details will follow)


TUESDAY October 10, 2017

Topics mixed from previous course #87 and 88:

ETCHING FUNDAMENTALS

- Pattern transfer in plasma etching

- Profile control for plasma etching

- Monitoring and controlling a plasma etching processes

(more details will follow)

 

WEDNESDAY October 11, 2017

PLASMA ETCHING FOR FRONT END OF LINE APPLICATION

- Photoresist and mask

- Poly silicon gate etching

- Metal gate / High-k etching

- Atomic Layer Etching

- New patterning technologies

- New transistor architectures

(more details seen below)

THURSDAY October 12, 2017

PLASMA ETCHING FOR BACK END OF LINE APPLICATION

- Etching with a fluorocarbon-based plasma

- Spacers etching

- Contacts etching

- Dense SiOCH etching for interconnects

- Porous SiOCH etching for interconnects

- High aspect ratio structures etching

(more details seen below)

TECHNOLOGY FOCUS
Extensive efforts to miniaturize semiconductor devices is largely attributed to lithography and etching technologies that allow semiconductor thin films patterning in the range of dimensions determined by the semiconductor road map. During more than 30 years, classical materials, such as aluminum, SiO2, and poly-silicon, have been integrated in semiconductor devices.


Nowadays, the technology imposes to work with new materials at each technological node. The integration of new high k and low k dielectric materials, metals at the front and back end of device fabrication, bring on new problem categories. This imposes the necessity to quickly build up expertise at a rate unprecedented in all the history of semiconductor manufacturing.

COURSE CONTENT AND OBJECTIVES
This course is intended to provide an understanding of plasma processes for CMOS applications and ULSI technology. We will discuss fundamental and practical aspects of front end and back end plasma processes for deep submicron CMOS logic processes.
The course is based on experimental results obtained using commercial etchers connected to very powerful diagnostics of the plasma and the plasma surface interaction. The discussions cover several aspects of etch processes of materials integrated in advanced CMOS devices, etch mechanisms, and situations that may be encountered for some important plasma processes.

Fundamental parameters obtained from advanced characterizations are used to discuss and analyze plasma etch processes. The emphasis is on real problems, fundamental understanding of processes used in manufacturing, considerations for integration with other steps, and issues brought by the fast device scaling.
Processes covered in detail include silicon gate patterning and all the problems related to critical dimension control as well as results on metal gate and high k dielectric etching. The etch processes associated with the integration of low k materials will be extensively discussed.

 

PREVIOUS 3-DAY COURSE OUTLINE:

Wednesday

Fundamentals in Plasma Processing

  • Ion Neutral/Synergy
  • Impact of Neutral Flux to Ion Flux Ratio on Plasma Processes
  • Etch Anisotropy
  • Passivation Layer Formation in Plasma Processes
  • Temperature Effects in Plasma Etching
  • Microscopic Uniformity in Plasma Etching
  • Impact of Aspect Ratio on Etching Processes
  • Charging Effects in Plasma Etching
  • Impact of Reactor Wall on Plasma Processing
  • Micro-Trenching Formation
  • Pattern Profiles

Thursday
Front End Of Line Processes for CMOS Applications

  • Resist Curing
  • Photoresist Trimming
  • Hard Mask Opening
  • Silicon Gate Etching
  • Thin Gate Oxide Behavior during Gate Etch Processes
  • Silicon Recess during Gate Etch Processes
  • Metal Gate Etching
  • Line Width Roughness Evolution
  • Chamber Wall Coating during Si/Metal/High K Etching
  • Chamber Wall Cleaning Strategies for CMOS Applications
  • Spacer Etching
  • New Challenges Associated with New Devices Architectures

Friday
Middle and Back End Of Line Processes for CMOS Applications

  • Etching Mechanisms in Fluorocarbon Plasmas Etching
  • Contact Holes Etching
  • Dense Low-k Etching Mechanisms
  • Patterns Transfer in Dense Low-k
  • Challenges Associated With Porous Low-k
  • Porous Low-k Etching Mechanisms
  • Porous Low-k Modification
  • Porous Low-k Patterning with an Organic Mask
  • Porous Low-k Patterning with a Metal Hard Mask
  • High Aspect Ratio Patterns Etching

 

citattecken

 

Said about the course from previous participants:
"Thank you very much for helping me make some sense of all the different types of etches and etchants. It will be invaluable."
"Good explanations for daily problems I face in my work."
"Excellently compiled topics with structure."
"Summaries of difficult topics, really new topics are introduced."



 
Length: 4 days
Regular Course Fee: 2695 euro
Early Course Fee: 2425 euro
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