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With continuing device scaling beyond the 32nm node, wiring interconnect becomes increasingly important in limiting chip density and performance. Fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing SiO2.The integration of these two advanced materials results in significant reduction in signal delay, cross-talk, and power dissipation, enabling the semiconductor industry to continue device scaling. The fabrication of Cu/low-k interconnect stacks requires novel materials and processes, including electroplating Cu, dual damascene structures, chemical-mechanical polishing, ultra-thin barriers, and passivation layers. These novel materials and processes give rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low-k interconnect stacks. As the technology continues to advance, the implementation of porous low k dielectrics brings in new processing and reliability issues, such as pore sealing, etch damage and ultra-thin barriers. These problems will be discussed together with recent advances in material and process development and reliability improvement for Cu/low-k interconnect stacks, including chip-package interaction. The 3D TSV integration process provides new challenges for processes (wafer thinning, TSV etch and fill), materials (materials compatibility, microstructure) and reliability (particularly stress-induced effects). This emerging field in microelectronics will be one of the key topics of the course.
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