Electronic and Photonic Devices

05  Current and Next Generation Lithography - Fundamentals and Applications
The explosive growth in the capability of semiconductor devices has to a large extent been due to advances in lithography. Miniaturization has enabled both the number of transistors on a chip and the speed of the transistor to be increased by orders of magnitude. At the same time, one has managed to reduce the power per transistor so that the chips do not overheat. This trend still continues uninterrupted. Sustaining Moore's Law requires continuous advancements in lithographic resolution. 
16  CMOS/BiCMOS Process Integration and Engineering
CMOS is the dominant integrated circuit technology offering low power consumption, ease of circuit design, and increasingly high performance with device scaling. BiCMOS adds the further advantages of noise immunity, linearity, device matching, and high drive capacity, thus permitting performance optimization and a higher degree of system integration. Hundreds of complex and mutually interdependent processing steps must be performed in a well-defined sequence in order to build the circuits successfully. These steps, as well as their sequence, must be carefully planned to assure high yield, adequate performance, and acceptable cost. 

36  Silicon Device Technology: Materials and Processing Overview
The rapid growth of the semiconductor industry has relied on the continual evolution of materials and processing compatible with fabricating modern silicon-based integrated circuits. Several technologies are emerging to meet the demands for higher speed and density, and lower voltage integrated circuits. Silicon-on-Insulator (SOI) technology with both Separation by Implantation of Oxygen (SIMOX) and wafer bonding approaches are now commercially available. 
37  Micro Fabrication Technology for MEMS and NEMS
In Micro Electro Mechanical Systems (MEMS), and Nano Electro Mechanical Systems (NEMS), both electrical and mechanical devices are formed. Often, the mechanical devices consist of movable components that are partially separated from the substrate they are anchored to. In some cases, special films with unique properties for sensing or mechanical movement are needed. Although the basic principles of the IC technologies used in silicon can be applied, there are many unique requirements for MEMS fabrication.

61  IC Reliability, Yield, Failure Analysis, and Fault Isolation
Reliability, failure analysis and yield are three of the cornerstones of a successful IC manufacturing technology along with product performance and cost. Many factors contribute to the achievement of high yield and reliability, and many of these also interact with product performance and cost.
A fundamental understanding of failure mechanisms and yield limitations enables the up-front achievement of these technology goals through circuit and layout design, device design, materials choices, process optimization, and thermo-mechanical considerations. Failure isolation and analysis, defect analysis, low yield analysis, and materials analysis are critical methodologies for the improvement of yield and reliability. Coordination of people in many disciplines is needed in order to achieve high yield and reliability. Each needs to understand the impact of their choices and methods on the final product. Unfortunately, very little formal university training exists in these critical areas of IC reliability, yield, and failure analysis.
75  Chip Interconnection Technology and Process Integration
With continuing device scaling, wiring interconnect becomes increasingly important in limiting chip density and performance. The evolution of the interconnect technology brings forth new and increasingly stringent materials and processing requirements. The driving forces that dictate the materials and processing requirements of metallization systems for high density circuits will be examined, emphasizing the current approaches used for Al-based and Cu-based interconnect development. As the device technology continues to advance, the interconnect development presents significant challenges for materials, process integration and reliability. Discussions will include interconnect development for specific applications, such as power devices and automotive modules.
87  Plasma-Assisted Etching and Reactive Ion Etching Using High and Low Density Plasmas
Plasma-assisted etching is used in many technologies. It is most critical in ultra large scale integrated (ULSI) circuit fabrication and is used many times during the processing of a single wafer. Other areas that rely heavily on plasma-assisted etching include micro-electrical-mechanical (MEMS) structure fabrication, many so-called nano-science processes, micro-optical and photonic activities and numerous other material processing where near room temperature chemical reactions are required. 
88  Plasma Etching for CMOS Technology and ULSI Applications
Extensive efforts to miniaturize semiconductor devices is largely attributed to lithography and etching technologies that allow semiconductor thin films patterning in the range of dimensions determined by the semiconductor road map. During more than 30 years, classical materials, such as aluminum, SiO2, and poly-silicon, have been integrated in semiconductor devices. 

Nowadays, the technology imposes to work with new materials at each technological node. The integration of new high k and low k dielectric materials, metals at the front and back end of device fabrication, bring on new problem categories. This imposes the necessity to quickly build up expertise at a rate unprecedented in all the history of semiconductor manufacturing. 

95  On-Chip and 3D Interconnect Technology - Processing and Reliability of Cu/Low-k and 3D Interconnects
With continuing device scaling beyond the 32nm node, wiring interconnect becomes increasingly important in limiting chip density and performance. Fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing SiO2.The integration of these two advanced materials results in significant reduction in signal delay, cross-talk, and power dissipation, enabling the semiconductor industry to continue device scaling. 

The fabrication of Cu/low-k interconnect stacks requires novel materials and processes, including electroplating Cu, dual damascene structures, chemical-mechanical polishing, ultra-thin barriers, and passivation layers. These novel materials and processes give rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low-k interconnect stacks. 

As the technology continues to advance, the implementation of porous low k dielectrics brings in new processing and reliability issues, such as pore sealing, etch damage and ultra-thin barriers. These problems will be discussed together with recent advances in material and process development and reliability improvement for Cu/low-k interconnect stacks, including chip-package interaction.

The 3D TSV integration process provides new challenges for processes (wafer thinning, TSV etch and fill), materials (materials compatibility, microstructure) and reliability (particularly stress-induced effects). This emerging field in microelectronics will be one of the key topics of the course.
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