CMOS/BiCMOS Process Integration and Engineering - CEI-Europe
Course #16

CMOS/BiCMOS Process Integration and Engineering

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

CMOS is the dominant integrated circuit technology offering low power consumption, ease of circuit design, and increasingly high performance with device scaling. BiCMOS adds the further advantages of noise immunity, linearity, device matching, and high drive capacity, thus permitting performance optimization and a higher degree of system integration. Hundreds of complex and mutually interdependent processing steps must be performed in a well-defined sequence in order to build the circuits successfully. These steps, as well as their sequence, must be carefully planned to assure high yield, adequate performance, and acceptable cost. 

This course has a threefold emphasis: first on understanding MOS and bipolar device requirements for current and future generations; second, on how integrated process sequences can be constructed to meet those requirements; and finally, on the subsequent needs for unit processes, such as enhanced mobility channels, gate stack formation, SiGe bases, lithography, shallow junction formation and multilevel metallization techniques - all crucial to successful submicron device implementation. 

Engineers and scientists working on the design, fabrication, and manufacturing of advanced silicon devices would benefit from this course. It provides an excellent way to obtain in-depth knowledge for those individuals who already have an engineering background but are relatively new to semiconductor process technology. Experienced participants, who are responsible for process development, will benefit from the years of problem-solving experience that are supplied by the instructor in his lectures and course notes. The course is also designed to provide management-level perspective on future trends and important issues in the semiconductor industry, as portrayed in the International Technology Roadmap for Semiconductors. 

CMOS Device Design and Optimization 
The challenges encountered in designing and fabricating semiconductor devices suitable for advanced ULSI are described. Basic semiconductor physics are reviewed starting from energy bands and doping in semiconductors and including pn junction and MOS operation. Short channel effects in state-of-the-art CMOS devices are described along with the tradeoffs between drive current, off-state leakage, and substrate current that are associated with alternative channel and drain doping strategies. 

CMOS device and circuit considerations to minimize device degradation are covered, including that caused by hot electrons and holes, and the electric field reduction options to minimize device degradation. The inherently bipolar nature of the CMOS structure and the latchup problem and its prevention are reviewed. Roadmaps are used to portray the advances of technology and to project future requirements. Strategies for future non-classical CMOS, including fully depleted and multi-gate FinFETs are shown. 

Bipolar Device Design and Optimization and BiCMOS Process Integration 
An extensive tutorial is given on bipolar transistor physics, device design, trade-offs, and optimization in an integrated BiCMOS process. 

Low- and high-level injection conditions are discussed. Key NPN and PNP DC and AC parameters are defined and their characterization described. These include gain, early voltage, ideality, capacitances, breakdown voltages, parasitic resistances and capacitances, gain-bandwidth product (ft), maximum oscillation frequency (fmax), and noise. The relation of parameters to horizontal and vertical geometries and their sensitivities to process variations are discussed. 

The objectives and considerations in integrating MOS and bipolar devices in BiCMOS technology are reviewed in detail. Process and device architecture alternatives and scaling schemes are reviewed for various silicon-based technologies. CMOS and bipolar device performance tradeoffs inherent in creating a BiCMOS process from purely CMOS or bipolar flows are addressed.   Emphasis is given to critical bipolar process modules such as buried layers, collector structures, vertical and horizontal isolation schemes, base formation, and polysilicon emitter design. SiGe and SiGe-C technologies and their advantages for analog/RF applications are reviewed. Integration of analog/RF passive components, their key parameters and characterization are discussed. 

Front End Processes: Active Device Formation

  • Buried Layers, Epi, Contacts to Buried Layers, and Well Formation Options
  • Shallow and Deep Trench Isolation and LOCOS Options
  • Formation of MOS and Bipolar Active Devices: Strained channels for 
    enhanced mobility, base and channel doping
  • Ultra-Thin Gate Insulators: Progression from SiO2 to SiON to high k
  • Poly-Si and Metal Gate Electrodes and Base/Emitter Contacts
  • Patterning: Lithography and etching

Applications of Ion Implantation and Rapid Thermal Annealing in CMOS/BiCMOS

  • Typical Ion Implants and Device Structures: From shallow source/ 
    drain extensions to deep wells, and their functions
  • Series Resistance Requirements for Contacts and Junctions: Xj-Rs needs
  • The Drain Extension Structure
  • Implant Considerations in Devices: Edge effects, shadowing, knock on
  • Control of Short Channel Effects with Channel and Halo Implants
  • Ion Implantation for Non-classical CMOS Devices, i.e., SOI and FinFET
  • Process and Device Simulation

Front End Processes: Junction and Contact Formation

  • Ultra-Shallow Junction Formation
  • Junction Contacting Strategies, Self-Aligned Silicides
  • Parasitic Series Resistance


  • Back End Processes: Multilevel Interconnect
  • Pre-Metal and Interlevel Dielectric Layers
  • Contacts and Vias
  • Planarization Strategies
  • Multilevel Interconnect Options

BiCMOS Yield and Reliability Considerations

This lecture covers systematic and random defects, yield models, critical areas, monitors, and yield management. Basic reliability concepts and models, including reliability distributions, acceleration factors and burn-in, are described to compliment earlier discussions of the reliability physics involved with electro-migration, hot-carrier effects, NBTI, oxide degradation and integrity, and latch-up.

citatteckenSaid about the course from previous participants:
"Very good coverage of both state of the art and conventional process technologies. Good notes for future reference."
"Very good Instructor, with a very broad knowledge, especially from industry."
"The course is advanced as well as introductory and gives a good overview of older and leading edge techniques."
"The topics were covered in great detail and the lecture notes were easily understood."

CEI-Europe AB, Teknikringen 1F, SE-583 30 Linköping, Sweden Phone +46-13-100 730 Fax +46-13-100 731