On-Chip and 3D Interconnect Technology - Processing and Reliability of Cu/Low-k and 3D Interconnects

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

(Previously this course was called Copper Low-k Interconnect Technology - Processing and Reliability of Cu Low-k Interconnect Metallization)

TECHNOLOGY FOCUS 
With continuing device scaling beyond the 32nm node, wiring interconnect becomes increasingly important in limiting chip density and performance. Fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing SiO2.The integration of these two advanced materials results in significant reduction in signal delay, cross-talk, and power dissipation, enabling the semiconductor industry to continue device scaling. 

The fabrication of Cu/low-k interconnect stacks requires novel materials and processes, including electroplating Cu, dual damascene structures, chemical-mechanical polishing, ultra-thin barriers, and passivation layers. These novel materials and processes give rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low-k interconnect stacks. 

As the technology continues to advance, the implementation of porous low k dielectrics brings in new processing and reliability issues, such as pore sealing, etch damage and ultra-thin barriers. These problems will be discussed together with recent advances in material and process development and reliability improvement for Cu/low-k interconnect stacks, including chip-package interaction.

The 3D TSV integration process provides new challenges for processes (wafer thinning, TSV etch and fill), materials (materials compatibility, microstructure) and reliability (particularly stress-induced effects). This emerging field in microelectronics will be one of the key topics of the course.

COURSE CONTENT 
This course will provide an overview of the materials, processes, and reliability for Cu/low-k and 3D TSV interconnects. It will focus on basic issues relating to copper deposition, damascene structure and processing, and wafer thinning and TSV etch and fill as well. Materials-related challenges and reliability issues will be discussed.

Wednesday pm - EHRENFRIED ZSCHECH
COPPER METALLIZATION AND LOW-K DIELECTRICS
We begin with an overview of interconnect scaling trends, problems, and potential solutions. We then provide a detailed discussion on current developments and processing integration of low-k dielectrics. Key areas discussed include chemical bond and electron polarizability and how they are optimized to yield desired properties for low-k dielectrics. Discussions on process integration include deposition and etching of low k dielectrics and the formation of ultra-thin liners in damascene structures. The impact of key process steps on performance and reliability of the final product will be highlighted and discussed. 

Copper Interconnect Technology

• Interconnect Scaling Trends, Interconnect Roadmap
• Performance and Density Limitations
• Wiring Design of Cu Interconnects
• Need for Advanced Materials
• Cu Damascene Interconnect Structures

Low-k Materials Properties and New Developments

• Dielectric Constant and Chemical Bond
• Molecular Design of Low-k Dielectrics - PECVD and Sol Gel Materials
• Fully Dense and Porous Low-k Dielectrics
• Electrical and Mechanical Properties
• Ultra Low-k Dielectrics with Improved Properties

3D integration

• Integration Approaches
• Through-Silicon Via Processing
• Materials-related Challenges
• Chip-Package Interaction

Thursday - JEFFREY GAMBINO
PROCESS INTEGRATION
In this section we focus on process integration, including dielectric deposition, patterning, metal deposition, and CMP.  We will also discuss basic packaging processes.  

PROCESSING OF COPPER LOW-K INTERCONNECT STRUCTURES

Dielectric Deposition

• Dielectric Selection
• Spin on Processes
• CVD deposition
• Post Deposition Processing
• Solvent Removal, Porogen Removal, Curing
• Characterization of Deposited Films
• Porosity, Thickness, Composition, Bonding

Dielectric Etching

• Via First vs. Line First Dual Damascene Schemes
• Hardmask vs. Softmask Processes
• Resist Poisoning
• Etch Control
• Resist Erosion, Line-edge Roughness, Profile Control
• Impact of Etch Processes on Dielectrics
• Lateral Etching, Low-k Oxidation
• Hybrid Structures

Liner Deposition

• Liner Selection
• Precleans and Damage Removal
• Wet Cleans
• In-situ Cleans
• Metal Deposition Options
• PVD Processes
• ALD Processes
• Resistance Impact and Liner
• Thickness Uniformity and Control
• Pore Sealing

COPPER DEPOSITION AND CHEMICAL MECHANICAL POLISHING
Copper Deposition

• Deposition Options
• Deposition Seeding
• PVD
• Alternative Seed Processes
• ALD, CVD, Electroless Plating
• Copper Electroplating
• Role of Additives
• Super Filling of High Aspect Ratio Structures
• Post Annealing and Line Resistance Control
• Electroless Deposition of Refractory Metals

CMP, Chemical Mechanical Polishing

• Damascene Processing
• CMP Slurries
• CMP Pads
• CMP Process Problems
• Erosion, Dishing, Corrosion, Scratches, Residues
• Alternative Planarization Processes
• Electropolishing, E-CMP
• Effect of CMP on Low-k Dielectrics
• Post-CMP Cleaning

Packaging Processes

• Dicing
• Wirebond Process
• Flip Chip Process

3D integration

• Applications
• Integration approaches
• Through-silicon via processing
• Temporary bonding / handle wafers
• Backside grind and polish
• Backside lithography / alignment
• Permanent Bonding approaches

Friday - EHRENFRIED ZSCHECH
RELIABILITY
We will now focus on reliability issues of Cu/low-k interconnect structures damascene structures. This will include thermal stress, electromigration, and leakage current characteristics. Recent advances in improving Cu/low-k reliability will be discussed, including the use of metal overlayers to improve adhesion and electromigration performance. For 3D IC integrated structures, stress-induced effects which enhance risk to fail for BEOL structures and new phenomena connected with 3D TSV integration will be discussed.. 

Structural Integrity and Reliability of Cu/Low k Interconnect Stacks and 3D TSV Structures

• Electromigration, Stress Migration, Time-dependent Dielectric Breakdown
• Microstructure and Inteface Effects and Characterization
• Materials and Geometry Effects, Thermomechanical Deformation
• Thermomechanical Stress in 3D IC Structures, Stress Engineering
• Chip-Package Interaction and New Phenomena
• Stress Induced Void Formation and Electromigration, TDDB in 3D IC Structures
• DFR and Multi-scale Simulation and Multi-scale Materials Data
• Process Control and Quality Control

Said about the course from previous participants:
"Small class, ability to ask questions. Professor Ho even changed part of his program to suit our questions."
"Various parts and the exhaustive view of the back-end technology of new material and processing techniques."
"Real aspects: issues/improvement in fabrication. "

See also course #75 Chip Interconnect Technology and Process Integration,
a 2.5 day course, which is conveniently scheduled before this course.