Data Converter Modeling, Simulation and Test

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

NEW COURSE FOR THE FALL OF 2012

Please Note! The course starts on the Thursday.

TECHNOLOGY FOCUS
Data Converters suffer from a wide range of non-ideal effects such as mismatch, parasitics, finite gain / bandwidth / slew rate, offset, noise and so on and so forth. Many of these effects are random effects of statistical nature. They also depend on first and second order characteristics of the process technology, layout, packaging, pinout etc. It is practically impossible to describe all these effects for all possible architectures, sizings, layouts on device ("SPICE") level and to compare all the simulation results to decide on the best implementation.
It is thus necessary to build higher level models which include all relevant effects, at least in the first order, but are still simple enough for quick modifications and efficient study of various layouts, topologies etc. Simulation times must not go beyond minutes. The relevant effects must, of course, be understood to be able to simplify and model them.

COURSE CONTENT
During the course the underlying basics and standards for Data Converter test methods will be presented. To give a deeper understanding of models and routines, the participants will work in pairs with hands-on programming and evaluation core routines. Finally, exemplary solutions will be given and discussed.

When Data Converter models are coded and simulated, when first samples of the new data converter come in, and finally during production, they have to be analyzed and their performance determined. Even if the converter should not be directly measured during production test, direct access and measurement is required for first characterization to establish correlations between analysis and production test, and in case of problems. Knowledge and understanding of the converter test methods is needed to choose the best approach, set up the test correctly, and avoid misunderstanding of the results.

WHO SHOULD ATTEND
This course is aimed at design, test and system engineers who need to model, simulate and/or test data converters or wish to improve their background in these topics. Pre-requisites for the course are a detailed understanding of data converter architectures and topologies together with some basic knowledge of analog circuit design. It is highly recommended that CEI-Europe course #12 "Embedded Data Converters" is attended before taking this course.

Attendee equipment:
A notebook with appropriate software (MATLAB with Control System, Signal Processing Toolboxes*, or OCTAVE with Control, Signal, Missing-functions Toolboxes**; preferably also SIMULINK ) is required to actively participate in the practical exercises. You will work in groups of 2 to 4 people.

Throughout the course MATLAB* compatible routines will be used. The last exercise uses SIMULINK*. It is not possible to offer the attendees a temporary MATLAB or SIMULINK license, however, the freeware program OCTAVE** can be used to code and simulate m-files (but not mdl-files).

Thursday
During the first day common converter test methods, strongly based on an IEEE standard for ADC test, will be explained. The attendees will receive a set of 'measured' data and program the core routines to evaluate them.

• DAC Test
• ADC Test
  o   Histogram Based Test
  o   FFT Based Test
• "Hands-on" Exercises (group work)
• Exemplary solutions

Friday
Morning:
Mismatch, layout dependency, op amp and comparator impact will be presented and simple models will be introduced. Then these effects will be modeled and simulated for a FLASH ADC. The attendees will receive 'measured' data for evaluation and try to program the core routines. Exemplary solutions will be presented and discussed.

• Mismatch, offset
• Layout Dependency
• Nonideal Op-amps and Comparators
• Modeling of a FLASH ADC
• Hands-on Exercises
• Exemplary Solutions

Afternoon:
A design methodology for sigma-delta converters will be practically applied. For a practical example (audio ADC) the synthesis, based on Schreier's toolbox* (using MATLBAB or OCTAVE), will be followed by simulation based on Malcovati's toolbox* (this one uses SIMULINK). Rules of thumb for block parameters like op-amp gain give a starting point for our simulations. The results will be extensively discussed.

• SDM Design Methodology (short rehearsal of the CEI-Europe course #12 chapter)
• SDM Specification
• Synthesis
• Sizing
• Simulation

*  both available from The Mathworks file exchange,  http://www.mathworks.com/matlabcentral/fileexchange/