Phase Locked Loops for Wireless Communication Systems - CEI-Europe
Course #85

Phase Locked Loops for Wireless Communication Systems

November 13 - 15, 2017 . Barcelona, Spain

We recommend you to submit your preliminary or firm registration at least 4 weeks before course start to ensure a seat on the course.

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Phase Locked Loop frequency synthesizers are key building blocks in wireless communication systems. Today, the industry is making huge progress towards total integration into one piece of silicon together with other building-blocks needed for a complete radio, all with the goal to make wireless products affordable and comfortable in use.

The course enables engineers to understand the principles of PLL circuits and its applications and to design PLL synthesizers optimized for a given application. It introduces advanced technologies of frequency synthesis used in modern communication devices.  


Control Loop Basics 
Control loop basics are the foundation of any detailed PLL consideration. The concepts of open and closed loop gain, phase and amplitude margin and their link to the dynamical behaviour are introduced. The Z-transformation as a method to describe and optimize the behaviour of time discrete control loops is explained.

  • Open and Closed Loop Gain and Phase Transfer Function
  • Bode Plot, Phase Margin, Amplitude Margin
  • Poles and Zeros, Characteristic Function
  • Closed Loop Transfer Function, 3dB-Bandwidth, Dynamic Control Behavior
  • Describing Time Discrete Control Loops by Z-Transformation

Phase Noise in a Wireless System 
We introduce parameters that describe the phase fluctuations and establish relationships between different sets of parameters. The section is completed by a discussion of the impact of the noise behaviour of a PLL on the receiver and transmitter performance in a wireless system.

  • The Phase Angle as a Random Process
  • Parameters Describing Phase Fluctuations and Relations between them
  • SSB Phase Noise, Phase and Frequency Error
  • Effect of the Phase Noise on the Blocking and Adjacent Channel Power Performance

The Elements of a PLL
In this section we have a closer look at the components that build a PLL. All building blocks of a PLL are described in terms of their linear transfer functions.

  • VCOs
  • Phase Noise in VCOs
  • Phase Detector Types
  • Use of Op-Amps
  • Dividers and Mixers in a PLL

PLL Dynamical Behavior
Based on the linear description of the building blocks, we will derive the transfer functions of a PLL and their implications on the system performance such as switching time and spurious suppression. A discussion of the noise behavior of the PLL will complete this section.

  • The Phase Transfer Function
  • Transfer Functions for Noise and Spurious Signals
  • Lock Time, Natural Frequency, Damping Factor, and Phase Margin
  • High-order Loop Filters
  • Relationship between Phase Comparison Frequency and Loop Bandwidth 
  • Phase and Frequency Modulation in a PLL
  • Sources of Phase Noise in a PLL and its Simulation



Practical PLL Design Issues
This section deals with the practical design requirements of PLL synthesizers in a wireless system. As the loop filter is a key element in any PLL, its dimensioning based on lock time and spurious requirements will be treated in great detail. We will also discuss sources of phase detector spurs, speed-up circuits and the problems linked to it.

  • Loop Filter Dimensioning from Lock Time Requirements
  • Compromise between Spurs, Noise and Lock Time
  • Sources of PFD Spurs
  • Charge Pump Issues
  • Problems Linked to Speed-up Circuits
  • Fractional N PLLs
  • Spurs Due to the Concept of Fractionality
  • Compensation of Fractional Spurs
  • The Impact of Phase Detector Linearity

The Mesurement of PLL Parameters 
This section covers the measurement of PLL parameters from a practical point of view.

  • Phase Noise Measurement with a Spectrum Analyzer
  • Phase Noise Measurement by Down Conversion
  • Delayed Self Homodyne Phase Noise Measurement
  • Simple and High Precision Lock Time Measurement Methods
  • Measuring the PLL Phase Transfer Function



Sigma-Delta PLL

Starting from a classical PLL, the mathematical description of the noise behavior of a Sigma-Delta PLL with multi-modulus divider is developed. The digital fractional spurious compensation is modelled, and in a second step we perform a quantization noise simulation and extract rules of thumb helping the early architecture work. Frequency resolution and other key parameters are treated before advantages are summarized.

  • Sigma-Delta Modulator
  • MASH
  • Divider Control
  • Quantization Noise
  • SSB Phase Noise
  • Frequency Resolution
  • 2-point modulation


Direct Digital Synthesis

The architecture of a DDS is analyzed in detail. The noise and spurious response of the system is considered for each building-block. Other system parameters like lock-time and frequency resolution will be touched.

  • Accumulators
  • Phase and Amplitude Quantization
  • Frequency Resolution
  • Spurious Analysis
  • DAC

Complete Digital PLL - Digital Controlled Oscillator (DCO)

Silicon technology trends allow new PLL architectures and increase its digital content. Starting point is the analysis of a DCO and its application in a closed loop system. Means to increase frequency resolution and quantization noise will be treated on an architectural level.

  • DCO
  • Digital Loop Filter
  • All Digital Loop
  • Quantization
  • Non-linear Control Loop


Said about the course from previous participants:
"Practical examples and exercises."
"A lot of interaction, good depth in material."
"Practical measurements on hardware."
"The level of the course has been chosen correctly / properly matched with the audience level."
"Instructors with plenty of real-life practical knowledge."



CEI-Europe AB, Teknikringen 1F, SE-583 30 Linköping, Sweden Phone +46-13-100 730 Fax +46-13-100 731