Failure Analysis Manager, IBM Systems & Technology
Group, Burlington, VT, USA.
Mr. Vallett has over 25 years experience in CMOS
characterization and failure analysis and is currently in the
Worldwide Analytical Services Technology Quality Group.
He is widely published in the field, with four best-paper awards,
and has given a number of lectures on analytical technology
challenges in both micro and nanoelectronics. He holds fourteen US
patents and shared in IBM's Outstanding Technical Achievement award
for his contributions to picosecond imaging circuit analysis (PICA)
using time-resolved photon emission microscopy.
Mr. Vallett is a senior member of the IEEE, a member of
the Electronic Device Failure Analysis Society board of directors,
and belongs to Tau Beta Pi - the National Engineering Honor
Society. He is a past chair of the International SEMATECH Product
Analysis Forum and was selected as the 2008 General Chair for ISTFA
- the International Symposium for Testing and Failure
Analysis.
He presently manages a group responsible for technology development
and packaging failure analysis, silicon micromachining,
nanoprobing, X-ray tomography, and physical fault isolation using
magnetic field, photon emission, and laser scanning microscopy. Mr.
Vallett holds the BS degree in electrical engineering from the
University at Buffalo, New York, USA.
Mr Vallett has been a member of the CEI-Europe faculty since
2005.
Course #61
Yield and Reliability in VLSI Development and Manufacturing
Course #62
IC Debug, and Fault Isolation