News - CEI-Europe

On-Chip and 3D Interconnects

12/7/2015 12:00:00 AM

A spring 2016 date has been set for course

May 10 - 12, 2016. Dresden, Germany

Course Instructors: Professor Ehrenfried Zschech and Dr. Martin Gall

This course will provide an overview of processes, materials and reliability for on-chip and 3D TSV interconnects. It will focus on issues relating to manufacturing processes like dielectrics etch, copper deposition and damascene structuring of Cu/low-k stacks, as well as on wafer thinning and TSV etch and fill for 3D IC integration as well.

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CEI-Europe AB, Teknikringen 1F, SE-583 30 Linköping, Sweden Phone +46-13-100 730 Fax +46-13-100 731