April 08 - 12, 2019. Amersfoort, The Netherlands.

Dr. István Novák Senior Principle Engineer, Signal and Power Integrity, Oracle, Boston, USA is teaching this 5-day course in Advanced High-Speed Design and Characterization.

High-speed designs continue to undergo major technology changes. In recent years, parallel memory signalling rates are above 1000 Mbps and main-stream serial signalling is in the 5-10 Gbps range; signal rise and fall times shrink to way below 10 ps.

As a result, laminate and copper characteristics, glass-weave and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be understood and taken into account during the design process.

With the increasing utilization of transmit and receive equalizations, validation even with eye diagrams measured at package pins may not be sufficient in itself. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages and signalling levels come with reduced timing and noise margins.

The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects eventually link the previously independent power-integrity, signal-integrity and EMC design domains.

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Instructor Novak Element
Dr István Novák

Senior Principle Engineer, Signal and Power Integrity, Oracle, Boston, USA.

Dr. Novák is a Fellow of IEEE for his contributions to signal-integrity modeling, measurements and simulations. He has 40 years of experience in high-speed electronics designs as well as teaching and consulting.

Dr. Novák has been a member of the Continuing Education Institute-Europe faculty since 1992.

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Early Bird €2,925.00 Regular Price €3,250.00

Early Bird Price valid until: Feb 08, 2019