April 23 - 27, 2018. Amersfoort, The Netherlands.
High-speed designs continue to undergo major technology changes. In recent years, parallel memory signalling rates are above 1000 Mbps and main-stream serial signalling is in the 5-10 Gbps range; signal rise and fall times shrink to way below 10 ps.
As a result, laminate and copper characteristics, glass-weave and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be understood and taken into account during the design process.
With the increasing utilization of transmit and receive equalizations, validation even with eye diagrams measured at package pins may not be sufficient in itself. Today, equally challenging is the proper design of power distribution. A multitude of supply voltages and signalling levels come with reduced timing and noise margins.
The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects eventually link the previously independent power-integrity, signal-integrity and EMC design domains.