An FGPA consists of programmable integrated circuits that allow the logical functions performed to be updated through programming.

Understanding for the challenges that occur in FPGA projects, and the tools that handle the problems and tasks that you'll encounter is vital.

FPGA Development
FPGA Development


In this course, we will cover the tasks that are typical to an FPGA-project, including system design and the choice of a supplier and circuit family, the hardware considerations for integrating the FPGA circuit into the system, as well as the implementation and verification of the FPGA design.

The examples used in the course are from an actual project which was used to investigate typical program structures and best practices. They are written in VHDL, but the course isn't geared towards teaching a particular language, and so a certain grasp of VHDL or other HDL-languages is beneficial.

After completing the course, you'll have an understanding for the challenges that occur in FPGA projects, and the tools to handle the problems and tasks that you'll encounter.

You've learned:

  • The basic structure of the FPGA circuits on the market.
  • The product offerings of the major suppliers with insight into characteristics such as price, performance, and special functionality, as needed to make an informed choice of FPGA for your project.
  • Hardware considerations such as pinout, voltage, signal integrity and power requirements.
  • Migration options for within various circuit families.
  • Clocking structures.
  • Performance and techniques for timing closure.
  • Implementation.
  • Verification, simulation, regression testing and target testing.
  • Debugging techniques and troubleshooting.
  • Best practices for constructing common components.
  • Techniques for maximizing efficiency, code quality and reuse.


Hardware developers with experience in digital circuit design looking to expand their knowledge about FPGA's.

System integrators looking for a deeper understanding of FPGA's and FPGA development.

Participants are expected to have experience in hardware development and a basic understanding of a Hardware Description Language such as Verilog or VHDL.

FPGA Development

Day 1

  • FPGA Concept Refresher
  • VHDL Basic Refresher
  • Configuration Techniques
    • OTP/FLASH/SRAM based configuration methods
    • Program storage
    • Configuration time aspects
  • Hard FPGA Macros
    • Useful hardware structures in addition to LUT/FF fabric of the FPGA such as Clock distribution and regeneration
    • PLLs/DLLs
    • BlockRAM
    • DSP modules
    • Gigabit transceivers

Day 2

  • Soft FPGA Macros
    • Configurable building blocks (FIFO, RAM, ROM, Arithmetics etc.) through tools like Xilinx Core Generator or Altera MegaWizard
    • 3:rd party Intellectual Property (IP) modules
  • Code Entry
    • Various code entry aspects
    • Graphical design entry contra text editors
    • VHDL/Verilog templates etc
  • Test Benches for Verification in Simulation
    • Self-checking test benches
    • Modelling of surrounding modules
  • Constraint Files
    • Pin locking and IO standards
    • Timing constraints

Day 3

  • Implementation
    • Logic synthesis
    • Place & Route
    • Configuration file generation
  • Timing Closure
    • Predictable routing results
    • Pipeline of complex functions
    • Geometric pipelining
    • Guide files
    • Floor planning
  • Target Test
    • Verify the design on actual hardware
    • Test structures
  • Debugging
    • Using test muxes with external logic analyzers contra built in analyzers such as ChipScope/SignalTap etc