With the continuous scaling down of semiconductor devices, interconnect technology and advanced packaging including TSVs become increasingly challenging for product performance and reliability. For on-chip interconnects, fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing SiO2. The integration of advanced materials, including barriers, results in significant reduction in signal delay, cross-talk and power dissipation, enabling the semiconductor industry to continue device scaling.

The manufacturing of Cu/low-k interconnect stacks requires new processes, including dual damascene patterning, Cu electroplating and chemical-mechanical polishing, as well as deposition of ultra-thin barriers and passivation layers. These novel materials and processes have to be understood to achieve high manufacturing yield and to mitigate product reliability issues. Electromigration and stress-induced voiding in Cu interconnects will be discussed. The integration of porous low-k dielectrics provides new processing and reliability challenges. These issues will be discussed together with recent advances in material and process development, as well as time-dependent dielectric breakdown for Cu/low-k interconnect stacks and chip-package interaction.

The 3D TSV integration process provides new challenges for processes (wafer thinning, TSV etch and fill), materials (materials compatibility, microstructure) and reliability (particularly stress-induced effects). This emerging field in microelectronics will be one of the key topics of the course. The role of multi-scale modelling and simulation as well as the need of accurate multi-scale materials parameters will be addressed in particular.

Technological trends and specific applications like mobile communication and connectivity, as well as applications in automotive industry, will be discussed.

On-Chip and 3D Interconnects
On-Chip and 3D Interconnects


This course will provide an overview of processes, materials and reliability for on-chip and 3D TSV interconnects.

It will focus on basic issues relating to manufacturing processes like dielectrics etch, copper deposition and damascene structuring of Cu/low-k stacks, as well as on wafer thinning and TSV etch and fill for 3D IC integration as well.

Materials-related challenges, reliability issues and emerging applications will be discussed.

The course will include interconnect systems development for specific applications, such as mobile and automotive applications.

Technology trends of interconnect architecture for future microelectronic products will be discussed.


This course is intended for engineers, particularly in technology development, process engineering as well as yield and reliability engineering,  both in industry and academia, as well as all who wish to expand their knowledge in the materials, processing and reliability aspects of metal interconnects and advanced packaging of microelectronic products.

On-Chip and 3D Interconnects

Day 1

Trends in interconnect technology and performance challenges

The scaling of integrated circuits and the impact on performance and density of interconnects will be reviewed. Past and future trends in interconnect development and the ITRS technology roadmap will be presented. Key issues for controlling interconnect density and performance will be examined, including effects of device scaling and wiring optimization. New on-chip interconnects stacks with copper interconnects and low dielectric permittivity (low-k) materials as well as advanced packaging including 3D integration of chips will be introduced.

On-chip interconnects: Processes and materials

Multilayered interconnect structures designed to achieve high density and high performance will be discussed. Al metallization technology will be compared with Cu metallization technology, processes using the damascene patterning and chemical-mechanical polishing will be reviewed. Barrier layers and deep trench filling for on-chip interconnects will be described. Processes for 3D interconnect stacks, including silicon etch and through-silicon-via (TSV) fill as well as wafer thinning, and materials-related topics will be discussed.

Materials compatibility and thermomechanical stress

Advanced packaging including 3D IC integration requires the integration of multiple materials with specific properties. Different properties of the components provide thermo-mechanical stress in planar chips and in 3D IC stacks. Stress-induced effects which enhance the risk to fail for on-chip and 3D interconnect structures and new degradation and failure mechanisms connected with 3D TSV integration will be discussed.

Day 2

Thin film materials properties: Metallization and dielectrics

Thermodynamic and kinetic aspects of thin film deposition will be reviewed. Various thin film deposition processes such as evaporation, sputtering, chemical vapour deposition (CVD), plasma-enhanced CVD, atomic layer deposition (ALD) of metals and dielectric thin films will be described. The relationship between deposition processes, stresses, microstructure, and various other materials properties in thin films will be presented. Examples will be taken from multilevel on-chip interconnects.

Backend-of-line stack reliability: Electromigration, stress-induced voiding, time-dependent dielectric breakdown

Major reliability issues for multilevel submicron interconnects will be discussed, focusing on electromigration and stress-induced void formation. Electromigration characteristics for Al and Cu interconnects will be compared, including damage mechanisms. The statistical approach for early failure detection in high-density interconnect systems will be presented. Stress-induced voiding will be discussed, emphasizing thermal stress behaviour in confined line structures. Furthermore, time-dependent dielectric breakdown mechanisms in Cu/low-k interconnect stacks will be reviewed.

Specific applications: Power electronics, automotive

Interconnect architectures for specific device applications such as power electronics and automotive modules will be discussed. Due to different device requirements such as high power consumption or elevated temperature usage, interconnect structures have to be tailored towards their specific applications. An overview of the various device types will be given and their impact on the choice of interconnect scheme will be discussed. The increasing role of reliability engineering, particularly for automotive applications, considering the whole supply chain will be explained.

Day 3

Performance and reliability issues in 3D stacked ICs, chip-package interaction

Thermo-mechanical stress in 3D TSV stacks provides the high risk of the degradation of the device characteristics for FETs that are located next to TSVs. Strain in the transistor channel changes the band structure and eventually the mobility of the charge carrier mobility and the transistor characteristics. In addition, interface delamination in Si/Cu-TSV structures and subsequent cracking are reliability concerns. Even more critical seems to be the chip-package interaction, i. e. the reliability-limiting crack propagation processes in Cu/low-k interconnect stacks, caused by the mechanical stress from the advanced packaging. This effect is particularly critical for porous ultra low-k dielectrics.

Multi-scale modeling and materials data

The application of physics-based models for a multi-scale simulation of mechanical stress in 3D TSV-stacked products has been proposed. Highly accurate multi-scale materials data are needed as input for this approach of simulation and for model validation. The set of materials data for wafer-level and package-level structures, needed to feed a materials database that comprises the input parameters for simulation, is discussed. Particularly the generation of materials data such as (local and effective) Young's modulus, Poisson ratio and (effective) coefficients of thermal expansion (CTE) on several scales will be described. TCAD simulations show significant influence of the copper microstructure on the charge carrier mobility in transistors.

For model validation and calibration, local stress measurements are needed to determine the effect of the TSV/package-induced stress on the transistor performance. Due to the high resolution needed, the only direct technique to measure strain in transistor channels is TEM.

Specific application: Mobile communication

Interconnect architectures for specific product applications such as smart phones will be discussed. Due to different product requirements such as small floor space, low power consumption and high bandwith, interconnect structures have to be tailored towards their specific applications.