Power distribution is becoming an increasing challenge in today's electronic designs, small and big alike.  Properly designed power distribution is essential also for good signal integrity and to avoid electro-magnetic interference problems.

Parallel memory bus speeds of 4800 to 5200MHz are becoming available and main-stream serial signalling is in the multi-Gbps range, high-end communications gears planning beyond 112 Gbps transfer speeds; signal rise and fall times shrink to below 10 ps. 

As a result, laminate and copper characteristics, surface roughness, glass-weave effects and glass structure, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be considered. With the increasing utilization of equalization and pre-emphasis, validations even with masks and eye diagrams may not be sufficient, giving way to Channel Operating Margin (COM) and Effective Return Loss (ERL).

Today, equally challenging is the proper design of power distribution. A multitude of different supply voltages and signalling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains.

Signal Integrity
Signal Integrity


This thoroughly updated and renewed unique course is based on decades of successful design experience of satellite circuits and high-end computer systems.  It provides a unified analysis and design approach to the power-integrity and signal-integrity disciplines with a brief overview of EMI-prevention tasks in modern digital systems that is necessary to understand the proper signal- and power-integrity design approaches. The course focuses on the most recent challenges that the digital and mixed analog/digital designers face, with an increased portion devoted to proven power distribution analysis techniques, design methods, solutions and practical details of component selection.  The course deals with the underlying physical rules with minimal mathematics. With interactive software and live hardware and software demo illustrations, the various good and bad design choices are explained and trade-offs are shown for achieving high-performance yet cost-effective designs.

For power distribution and EMC, the course explains the benefits and proper use of impedance profile of the bypass network, how it relates to time-domain design and validation methods and how to estimate and compare the worst-case transient noise of various PDN synthesis techniques. The key elements of long-term reliability and foundations of robust yet cost-effective designs are explained.  For high-speed signal transmission, emphasis is put on the dispersive and lossy nature of PCB and package traces showing the link between rise-time degradation, jitter, eye closure and the frequency-dependent dielectric constant, dielectric loss tangent and copper surface roughness. Link performance is explained in terms of S parameters, Channel Operating Margin and Effective Return Loss.

Participants will receive a free copy of the out-of-print popular book “Power Distribution Design Methodologies” and several of the illustration tools and simulation files shown in the class.


The course is aimed at engineers, scientists and managers facing the combined signal- and power-integrity challenges in electronics designs for the computer, communications, consumer, medical, defense or automotive industries.

Only basic understanding of electronic circuits is assumed, because the course is delivered through practical illustrations and examples and emphasizes the understanding of the underlying physics.

Whether you are already knowledgeable in circuit design or in the theory of signal and power integrity, you will find many useful tidbits and a solid explanation of the important disciplines.

Signal Integrity

Day 1,

Common Foundation of Signal and Power Integrity

  • Introduction to signal and power integrity
    • Comparing signal spectra, time and frequency-domain solutions
  • Reflections, matching, terminations
    • Characteristic impedance, phase and group delay, termination solutions
  • Time and frequency domain solutions, linear networks
    • S and Z matrices
  • Printed circuit board construction
    • What is important for signal and power integrity, selecting a good stackup

Examples, live HW and SW demos: Calculation of interconnect parameters, reflection, matching, signal bandwidth and spectra

Day 2, 

Crosstalk and Loaded Interconnects

  • Crosstalk and crosstalk-reduction in signal and power integrity
    •  Metrics in time and frequency domain
  • Differential interconnects
    • Effects of imbalance, mixed-mode S parameters, mode conversion
  • Effect of electrical loading and discontinuities
    • Impact of loading on high-speed traces and power planes
  • Discrete R-L-C components
    • Critical design parameters and reliability considerations

Examples, live HW and SW demos: Effect of capacitive loading on transmission bandwidth, designing for a specific crosstalk goal

Day 3, 

Losses, Discontinuities and Signal-integrity System Design

  • Conductor and dielectric losses, vias, discontinuities
  • How roughness impacts signal and power integrity, laminate selection, via models
  • Grounding, shielding and EMI rules
  • Importance of in-system interference, grounding in mixed-signal systems
  • Clock sources, drivers and distribution, spread-spectrum clock
  • Jitter and stability characteristics of various oscillators and PLLs, resonances
  • Signal distribution in systems
  • ISI, Eye Diagram, Peak Distortion Analysis, and Linear Network Solutions

Examples, live HW and SW demos: Termination and quarter- and half-wave resonances in clock networks

Day 4,

Power Distribution Design Methodologies

  • PDN design methodologies
  • Reverse Pulse Technique, impedance synthesis options, pros and cons of multi-pole, Big-V, DMB design strategies
  • DC power distribution
    • DC drop on planes, why sharp turns are bad at DC, too
  • Power converters and sources
    • Batteries, linear and switching regulators, transient response, output impedance, loop stability
  • PDN components and filters
    • Filter design process, transfer functions

Examples, live HW and SW demos: Simulation of bypass capacitor service area, output impedance and gain-phase plots of DC-DC converters

Day 5, 

Signal and Power Integrity Measurements and Modelling

  • Mid- and high-frequency bypassing with power-ground laminates
    • Inductance of vias, planes, selecting bypass capacitors
  • S-parameter models, simulations and de-embedding procedures
    • Creating signal- and power-integrity models
  • High power and high frequency measurement techniques
    • How to measure sub-milliohm impedances

Examples, live HW and SW demos: Anatomy of PDN resonances, reducing ground loop impact on signal- and power-integrity measurements

Said about the course from previous participants:

"Practical examples and experiments."

"The important trends/basics/criteria for designs."

"Real-world applications (as opposed to math)."

"The illustrations using hardware were great at bringing the theory together."

"The course has a broad approach to the subject."