054 Signal and Power Integrity: Advanced High-Speed Design and Characterization

Power distribution is becoming an increasing challenge in today's electronic designs, small and big alike.  Properly designed power distribution is essential also for good signal integrity and to avoid electro-magnetic interference problems.

Parallel memory bus speeds of 4800 to 5200MHz are becoming available and main-stream serial signalling is in the multi-Gbps range, high-end communications gears planning beyond 112 Gbps transfer speeds; signal rise and fall times shrink to below 10 ps. 

As a result, laminate and copper characteristics, surface roughness, glass-weave effects and glass structure, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be considered. With the increasing utilization of equalization and pre-emphasis, validations even with masks and eye diagrams may not be sufficient, giving way to Channel Operating Margin (COM) and Effective Return Loss (ERL).

Today, equally challenging is the proper design of power distribution. A multitude of different supply voltages and signalling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains.

This thoroughly updated and renewed unique course is based on decades of successful design experience of satellite circuits and high-end computer systems.  It provides a unified analysis and design approach to the power-integrity and signal-integrity disciplines with a brief overview of EMI-prevention tasks in modern digital systems that is necessary to understand the proper signal- and power-integrity design approaches. The course focuses on the most recent challenges that the digital and mixed analog/digital designers face, with an increased portion devoted to proven power distribution analysis techniques, design methods, solutions and practical details of component selection.  The course deals with the underlying physical rules with minimal mathematics. With interactive software and live hardware and software demo illustrations, the various good and bad design choices are explained and trade-offs are shown for achieving high-performance yet cost-effective designs.

For power distribution and EMC, the course explains the benefits and proper use of impedance profile of the bypass network, how it relates to time-domain design and validation methods and how to estimate and compare the worst-case transient noise of various PDN synthesis techniques. The key elements of long-term reliability and foundations of robust yet cost-effective designs are explained.  For high-speed signal transmission, emphasis is put on the dispersive and lossy nature of PCB and package traces showing the link between rise-time degradation, jitter, eye closure and the frequency-dependent dielectric constant, dielectric loss tangent and copper surface roughness. Link performance is explained in terms of S parameters, Channel Operating Margin and Effective Return Loss.

Participants will receive a free copy of the out-of-print popular book “Power Distribution Design Methodologies” and several of the illustration tools and simulation files shown in the class.

The course is aimed at engineers, scientists and managers facing the combined signal- and power-integrity challenges in electronics designs for the computer, communications, consumer, medical, defense or automotive industries.

Only basic understanding of electronic circuits is assumed, because the course is delivered through practical illustrations and examples and emphasizes the understanding of the underlying physics.

Whether you are already knowledgeable in circuit design or in the theory of signal and power integrity, you will find many useful tidbits and a solid explanation of the important disciplines.