Dr. István Novák, Principal Signal and Power Integrity Engineer, Samtec, Boston, USA, is teaching this 5-day course in Advanced High-Speed Design and Characterization.
Power distribution is becoming an increasing challenge in today's electronic designs, small and big alike. Properly designed power distribution is a key requirement to achieve good signal integrity and to avoid electro-magnetic interference problems.
In recent years, parallel signalling rates exceeded 1000Mbps and main-stream serial signalling is in the 5-10 Gbps range; signal rise and fall times shrink to below 10 ps.
As a result, laminate and copper characteristics, glass-weave and surface roughness, frequency-dependent trace and component parameters, inter-symbol interference (ISI), jitter and finite bit-error-rate (BER) all need to be considered. With the increasing utilization of equalization and pre-emphasis, validations even with eye diagrams may not be sufficient.
Today, equally challenging is the proper design of power distribution. A multitude of supply voltages and signalling levels come with reduced timing and noise margins. The allowed noise on signals and on supply rails decreases and the increasing density and bandwidth of interconnects inter-link the previously independent power-integrity, signal-integrity and EMC design domains.